lpcware

SCT camera interface LPC1800 (problem VGA configuration)

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by fabriziouser on Thu May 14 04:08:24 MST 2015
Good morning everyone,

my name is Fabrizio (sorry for my english). I would kindly ask for your help concerning a problem on interfacing between the MCB1800 board (LPC1857 single core) and the cam OV7670.
I'm working on application "SCT camera interface design with LPC1800 and LPC4300" (AN11365). Below the link where you can download the orignal firmware:

http://www.lpcware.com/content/nxpfile/an11365-sct-camera-interface-design-lpc1800-and-lpc4300

The original firmware works with the OV7670 configured in QVGA mode (320x240) with RGB565 format.

I'd like configure the cam in VGA mode (640x480) with YUV format and do a double buffering with "buffer1" and "buffer2" (stored in internal SRAM) each of which contains a line of the frame (640 pixel x 2 byte for YUV format = 1280 byte for each buffer).

I configured the camera with the following instructions:

// VGA, YUV422
ov7670_write_reg(0x12, BVOFF(4) | BVOFF(2) | BVOFF(0));

//Frame rate adjustment for 13 Mhz input clock (XCLK = 12MHz)
//30 fps, PCLK = 26Mhz
ov7670_write_reg(0x11, 0x00);
ov7670_write_reg(0x6b, 0x4a);
ov7670_write_reg(0x2a, 0x00);
ov7670_write_reg(0x2b, 0x00);
ov7670_write_reg(0x92, 0x2b);
ov7670_write_reg(0x93, 0x00);
ov7670_write_reg(0x3b, 0x0a);

I measured these signals with oscilloscope and are all correct.

Synchronization is based on signals vsync and hsync generated by camera. The rising edge of the signal vsync identifies the end of a frame (in this instant i configure the DMA to receive the first line of the new frame, transfer size 640 x 2 and address buffer1).
The falling edge of hsync identifies the end of a line and in this instant i configure the DMA to make a new transfer with sizes 640 x 2 but at address buffer2). These signals generate SCT interrupts and in this call back i call the function to initializa the DMA transfer. With buffer1 and buffer2 i use the double buffering technique where on each rising edge of vsync and each falling edge of hsync i re-configure the DMA to make a new transfer of 640 bytes x 2 alternating the two buffers. The request on DMA transfer is done from rise edge of PCLK. These signals are associated to events of SCT interface.

unsigned char buffer1[2*640];
unsigned char buffer2[2*640];
int toggle = 0;

void _prvInitCamDMAXferDir(void)
{  
//  s_ccb.pBuf = s_ccb.buf.a8;
    s_ccb.pCHN->CONFIG =
    //  Dis     | SrcPerp=SCT            | DstRAM | P->M    | XferDoneIrqEn
        0UL<<0  | YACB_SCTDMAPERIPNUM<<1 | 0UL<<6 | 2UL<<11 | 1UL<<15;
    s_ccb.pCHN->SRCADDR = (unsigned int )(LPC_GPIO_PORT->PIN + GPT_IMGD0);
   
    //s_ccb.pCHN->DSTADDR = (unsigned int) s_ccb.pFB;
    if(toggle == 0)
        s_ccb.pCHN->DSTADDR = (unsigned int) buffer1;
    else
        s_ccb.pCHN->DSTADDR = (unsigned int) buffer2;
   
   
    s_ccb.pCHN->CONTROL =
    //  size                | SBurst=1| DBurst=4| SWidth=8| DWidth=32| SMstr=1 | DMstr=0 | !SrcInc | DstInc  | Prvlg   | B,C      | EnInt
        2*640<<0     | 0UL<<12 | 1UL<<15 | 0UL<<18 | 2UL<<21  | 1UL<<24 | 0UL<<25 | 0UL<<26 | 1UL<<27 | 1UL<<28 | 3UL<<29  | 1UL<<31;
    s_ccb.pCHN->LLI = 0; //(unsigned int) s_ccb.lliAry[0].pNext;
   
    s_ccb.pCHN->CONFIG |= 1UL<<0;   // Enable chnnel
   
    toggle++;
   
    if(toggle > 1)
        toggle = 0;
}

When i go to read the buffers' content, "buffer1" contains the line completed (640 byte x 2) and it's ok, but "buffer2" no, it contains only half line (320 byte x 2) like a QVGA and i do not understand why.

I thinked a problem of XCLK and i have setted it to 24 MHz instead of 12MHz but the problem is remained.
Have you any suggestions to solve this problem? I don't understand the origin (SCT configurations, DMA configurations, timing, ....)

Thank you very much for your help.

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