I2S Slave with SGPIO

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by GH on Fri Nov 28 02:09:00 MST 2014

im working on the implementation of a I2S slave on the SGPIO peripheral of a LPC4337.
All in all it works, but from time to time I experience some synchronization problems.

All clocks are provided by external peripherals. I'm running all Slices with the external word clock (SCK).
Further I need to synchronize the Position Counters of the Slices with the word clock. Therefore I continuously read the REG value of the Slice connected to the WCLK pin and enable the other slices (connected to the data lines) when I read the expected pattern.

Sometimes the synchronization fails and position counters are activated to late, thus the data lines are misaligned to the WCLK by one bit. It seems like the timing is in someway unpredicted, when starting the slices using the CTRL_ENABLED register.
Usually I would expect the LPC4337 to be fast enough to perform this tasks, since it's running at 196MHz while the I2S bus is running at 3MHz (bit clock) with a 48kHz word clock.

See the code of the synchronization loop:

if(count>=MAX_SYNC_COUNT){return -1;}


Is this the right design pattern to implement such a synchronization to a external signal? Or are there other ways to implement such a task?

Thanks in advance for any help.