lpcware

BL & CL parameters in SDR-SDRAM

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by hamedb3269 on Sat Mar 14 01:17:15 MST 2015
hi
How BL and CL parameters to be determined?
i am using "4M*16bit*4banks" sdram.
CLK frequency = 120MHz

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