#define SGPIO_SLICE (10) // Slice J #define CMD_SGPIO_PIN (3) // Initialize the SGPIO interrupt (shared by shift/capture/match/input) NVIC_DisableIRQ(SGPIO_INT_IRQn); // clear interrupt status and wait for it to clear LPC_SGPIO->CTR_STATUS_1 = 0xffff; while(LPC_SGPIO->STATUS_1 & 0xffff); LPC_SGPIO->CTR_STATUS_2 = 0xffff; while(LPC_SGPIO->STATUS_2 & 0xffff); LPC_SGPIO->CTR_STATUS_3 = 0xffff; while(LPC_SGPIO->STATUS_3 & 0xffff); // disable all SGPIO interrupts LPC_SGPIO->CLR_EN_1 = 0xffff; while(LPC_SGPIO->ENABLE_1 & 0xffff); LPC_SGPIO->CLR_EN_2 = 0xffff; while(LPC_SGPIO->ENABLE_2 & 0xffff); LPC_SGPIO->CLR_EN_3 = 0xffff; while(LPC_SGPIO->ENABLE_3 & 0xffff); NVIC_EnableIRQ(SGPIO_INT_IRQn); LPC_SGPIO->CTRL_ENABLED = 0; // disable all counters // Configure pins /// See Table 187. Pin multiplexing Chip_SCU_PinMuxSet(1, 2, SCU_MODE_FUNC3 | SCU_PINIO_FAST); Chip_SCU_PinMuxSet(1, 16, SCU_MODE_FUNC2 | SCU_PINIO_FAST); //Connect SGPIO clock to Main_PLL Chip_Clock_SetBaseClock(CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false); LPC_SGPIO->OUT_MUX_CFG[CMD_SGPIO_PIN] = 0; LPC_SGPIO->SGPIO_MUX_CFG[SGPIO_SLICE] = 1 << 0 | // EXT_CLK_ENABLE 1 << 1 | // CLK_SRC SGPIO9 3 << 5 | // Qualifier mode : external clock 1 << 7; // Qualifier pin: SGPIO9 LPC_SGPIO->SLICE_MUX_CFG[SGPIO_SLICE] = (0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier) (0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock) (0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge) (0L << 3) | // INV_OUT_CLK = 0 (normal clock) (1L << 2) | // CLKGEN_MODE = 1 (use external clock) (0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge) (0L << 0); // MATCH_MODE = 0 (do not match data) LPC_SGPIO->POS[SGPIO_SLICE] = (32UL-1) | (32UL-1)<<8; //Reload value for POS (32) LPC_SGPIO->REG[SGPIO_SLICE] = 0x55555555; // Primary output data register LPC_SGPIO->REG_SS[SGPIO_SLICE] = 0x55555555; // Shadow output data register LPC_SGPIO-> GPIO_OUTREG = 0x00; // all pins input LPC_SGPIO -> SET_EN_1 = 1 << SGPIO_SLICE; LPC_SGPIO-> CTR_STATUS_1 = 0xFFFF; LPC_SGPIO->CTRL_ENABLED = (1 << SGPIO_SLICE); LPC_SGPIO->CTRL_DISABLED = ~( 1 << SGPIO_SLICE); |
if(LPC_SGPIO->STATUS_1 & (1 << SGPIO_SLICE)) { bits = 32; *ptr++ = LPC_SGPIO->REG[SGPIO_SLICE]; LPC_SGPIO -> CTR_STATUS_1 = 1 << SGPIO_SLICE; while( ! (LPC_SGPIO->STATUS_1 & (1 << SGPIO_SLICE))); } |