ADC details (sample time)

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by jpl90 on Tue Jun 07 12:36:02 MST 2016
I'm working with an LPC15xx and my application requires a kind of deep understanding of how the ADC works (timings). I've seen there is not enough info in the UM or the datasheet, so I'm asking here.

I've been reading some old threads which refer to or ask these questions, but I found two problems: The first one, as I mentioned, they are quite old. I'm not sure if the peripherals have changed in the last years or not. The second one, I couldn't find solid confirmation from some FAE about this matter (I even found posts which confused me even more! https://www.lpcware.com/content/forum/adc-sample-and-hold).

I've assumed the ADCs have a sample and hold principle, as some others state. That the ADC capacitor is charged for an "x" time, then that value (as an "image") is kept unchanged (no matter what the signal does after that moment) and measured for the rest of the time, until the conversion finishes and the value is stored in the peripheral registers.

I need to know what that "x" time is. I'm sure that's proportional to the ADC clock: if I lower the ADC clock, my measurement is much preciser, but it's not exactly practical having to slow the whole conversion down only because I need the sample time to be longer! However, the sample time can not be adjusted independently in LPC15xx, so I guess there is no solution to this...

Anyway, I could find a kind of workaround for my application if you could tell me exactly how many ADC clocks this sample time lasts. I mean, how long the signal has to be stable before the ADC takes the "image" and starts the conversion, so as to be able to change my signal immediately after this moment.

Could someone confirm me this? I will do some trial and error research, as some have already done, but it would be great to have official info about this matter.

Thank you very much!