I am trying use the UART CTI Interruption to detect if a message has been received.
I set the FIFO Trigger level to 8 bytes. So, when a message of length less than 8 bytes is received the CTI Interrut is generated, so all fine here. When a non-8bytes-multiple message is received (e.g.: 18 bytes) all fine too: one RDA Interrrupt with 8 bytes, another RDA Interrrupt with 8 bytes and one CTI interrupt with 2 bytes. The issue is when a 8bytes-multiple message is received. In this last case all interrupts received are RDA, because this fit right with FIFO length.
My question is if there is any way to workaround this feature of LPC, and always receive a CTI interrupt when 3.5 character timeout has reached.