A big problem with my 8548e board!!!

[wangbo]

I encount a big problem when I debug my 8548e board,if I config the LAWn to DRR,for example

writereg LAWAR0 0x80f0001c  #enable LAW0,DDR,SIZE:512M

writereg LAWBAR0 0x00000000 #LAW0 baseaddress:0

when I read a address beong to LAW0,I find the cpu corrupt, none registers except e500core's is available.have anyone encounted this problem.

thanks

[zhanghu]

I  encounted the same problem twice and found two reasons.

First, I encounted on MC8641D platform and found that the Vref  not supplied,which makes the DDR controller collapsing.

Second, on the MPC8548 platform, I found the DDR refresh recovery time configuration of the DDR_time_cfg_reg not satisfying the DDR2-chip's requirments, which makes the DDR initialization process fail. Maybe other DDR time configurations not satisfying can also make DDR controller collapsing.