I have checked the below said things in atleast four of the MCUs.The results were same.
The problem is, say some trim value is loaded into ICGTRM( SFR register) from Non Volatile 250kHz location.I check the Busclock value using CRO through MCLK pin which is configured to give Busclk/2 (SMCLK=0x11; ).
Ideally, I should get the frequency of 4 MHz in locked condition.But in practice the MCLK pin o/p is coming around 3.98--4.02 MHz. i.e. around +/- 0.5% deviation in the BUS CLOCK also the busclock is varying in that range(3.98--4.02 MHz) every instant.
During this bus clock variation observation on CRO(at the same room temperature),I saw the values of "LOCK" bit which was set indicating the MCU was in locked condition.Also the DCO Stable bit was set indicating DCO output was stable
Don't you think that in the 'locked' condition / DCO stable condition, the resulting bus clock should be 8 MHz( MCLK=4MHz).Why is the variation of 0.5%.
Is this normal to have the ICG LOCK bit to set even if there is a deviation of 0.5%?
What is the maximum devaition which the ICG module says its in LOCKed condition,beyond which it says its unlocked.
Waiting for your speedy reply,
Message Edited by Denn*** on 2008-04-10 04:02 PM