QG8 & P&E Debugger + Cyclone Pro + IIC

Discussion created by Guest on Mar 21, 2008
Latest reply on Mar 22, 2008 by Jim Donelson
I've got a QG8 and I'm trying to get data out of a 24LC512 EEPROM via the IIC bus interface. I send a start condition, the device code + r/w bit set, then 2 address bytes, another start condition, another device address + r/w bit clear, then turn off the TX bit and do a dummy read to get the clock going for the 1st byte. I then wait for the TCF bit to set and read the IIC data register, over & over until I have all the data I need from the EE. It all works fine now, but debugging it was a real bitch. It seems that when the debugger's Memory window is displaying addresses that cover the contents of the IIC registers (specifically the IIDR at $34), then whenever the debugger stops it reads the IICS and IIDR for display, which it's supposed to do. But this screws up the IIC transfer because the chip takes the debugger's IIDR read as its trigger to clock in the next byte. I've never experienced any problem of this sort before, and I've always been under the assumption that reads in DeBug mode do not behave the same as reads from user code, i.e., they were sort of invisible to the chip's peripheral systems. Have I been under an incorrect assumption all this time or am I looking at a bug in the chip?

Message Edited by Wingsy on 2008-03-21 04:21 PM