While it is true that a PLL has less frequency jitter, it also consumes much more power than an FLL.
You will not see a PLL on a low power chip.
A DZ is hardly a suitable replacement for a QG4 in a low power application.
Are you setting "low power" or "high gain" ? (see the HGO bit in the ICSC2)
At what rate does the output voltage need to change?
Could you change the parameters of your output filter to filter out the 2ms signal?
Is there a possibility that noise is getting into the oscillator?
Normally you are supposed to mount the xtal on a little ground plane, and it should be very close the the MCU. How are you filtering the supply lines?
Did you try the internal oscillator? You may actually see less jitter, as there may be less noise. If you are using the 32.768 xtal for time keeping, it is possible to run the CPU and PWM on the internal clock while running th RTI on the external clock for timekeeping purposes. While the RTI will running directly from the external oscillator will not have the FLL jitter, unfortunately the minimum tick will be 7.8125 ms, so you can do PWM at this rate very effectively. However this is fine for a clock as /128 is one second. You can also sleep and have the RTI wake for a time clock.