68S08QG4 Internal DCO jitter

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68S08QG4 Internal DCO jitter

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mbt
Contributor I
hi,all,
 
i'm  using the QG4  to generate a pwm  and filter the output with an active filter,
i hope get a stable voltage from that, but i got a unexpected signal which has a
perio about 2ms, it is unacceptable in my system. the PLL's reference frequency
is from the 32.768Hz crystal, i tested the jitter of the pwm output ,it is very huge,
could someone tell me how to reduce the jitter of the QG4's internal oscillator?
 
thank you!
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bigmac
Specialist III
Hello,
 
The operation of the FLL does intrinsically produce jitter by the way in which the DCO frequency is derived.  The data sheet specifies a maximum amplitude of 0.2 percent, when averaged over a 2 ms interval.  Over shorter averaging intervals, the average jitter could be larger.  However, the typical jitter can be much smaller, and is likely to be dependent on the relationship between the reference frequency and the DCO output frequency.
 
You might experiment by varying the DCO frequency by relatively small amounts to see whether it is possible to reduce the amplitude of the jitter and/or obtain a jitter repetition period that is less critical to your application.
 
If this is still problematic, your only choice for the QG4 may be to use a high frequency crystal, and bypass the FLL altogether.
 
Is the filter for the PWM signal an analog type?  If it happened to be a sampling type, there could possibly be other issues, dependent on the sampling frequency used.
 
What PWM frequency do you use, and what are the filter characteristics (cutoff frequency, number of poles, etc)?  What output ripple are you attempting to achieve?
 
Regards,
Mac
 
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fabio
Contributor IV
I agree with Bigmac,

That's why FS released some newer devices (such as the DZ series) with an MCG module. The MCG module provides an FLL and a PLL. The PLL option should produce less jitter than the FLL one.

Best regards,
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JimDon
Senior Contributor III
While it is true that a PLL has less frequency jitter, it also consumes much more power than an FLL.
You will not see a PLL on a low power chip.
 A DZ is hardly a suitable replacement for a QG4 in a low power application.

Are you setting "low power" or "high gain" ? (see the HGO bit in the ICSC2)

At what rate does the output voltage need to change?
Could you change the parameters of your output filter to filter out the 2ms signal?
Is there a possibility that noise is getting into the oscillator?
Normally you are supposed to mount the xtal on a little ground plane, and it should be very close the the MCU. How are you filtering the supply lines?

Did you try the internal oscillator? You may actually see less jitter, as there may be less noise. If you are using the 32.768 xtal for time keeping, it is possible to run the CPU and PWM on the internal clock while running th RTI on the external clock for timekeeping purposes. While the RTI will running directly from the external oscillator will not have the FLL jitter, unfortunately the minimum tick will be 7.8125 ms, so you can do PWM at this rate very effectively. However this is fine for a clock as /128 is  one second. You can also sleep and have the RTI wake for a time clock.







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