i.MX6 Solo X Maximum LVDS Resolution

[robertberringto]

I configured my DTS file for a resolution of 1080x1024p @ 60 Hz. This requires a pixel clock of 109.19 MHz. Once I pass the LVDS signal through a de-serialize I confirm the pixel clock is ~114.679 MHz, so within 5%.

When I read the Reference Manual, I see a Serializer clock limitation of 595 MHz. If I simply take my pixel clock of 109.19 MHz and multiply it by 7 (as implied by other threads Single Channel LVDS Display with 1920x1080@60Hz ), I get 764.33 MHz, which exceeds the specification.

I'm successfully getting video through my system. What gives?

By the way, I configured my DTS file for full 1920x1080p @ 60 Hz, and the system hung while loading the kernal.

[igorpadykov]

Hi Robert

with clock limitation of 595 MHz (595/7) :

in i.MX6Q (with two lvds channels) for larger resolutions it is necessary to use split

mode with patch

https://community.freescale.com/message/525359#525359

Best regards

igor

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[robertberringto]

igor,

Thanks for confirming my assumptions regarding the relationship between LVDS clock and pixel clock ... however, I have a Solo X at my desk where we are de-serializing the LVDS, and I'm getting 1080x1024p @ 60 Hz where my actual measured pixel clock is 114.679 MHz. Even if I use the target 109.19 MHz, multiply that by 7, and I get 764.33 MHz. This is on a single LVDS interface. That's nearly 30% over the specification!

Is the Solo X specification of 595 MHz simply a "max guaranteed" parameter for timing/temperature range/unit-to-unit production variance?

[igorpadykov · Accepted solution]

Hi Robert

right this spec is over PVT range, that is "max guaranteed" parameter for timing/temperature

range/unit-to-unit production variance.

~igor