I configured my DTS file for a resolution of 1080x1024p @ 60 Hz. This requires a pixel clock of 109.19 MHz. Once I pass the LVDS signal through a de-serialize I confirm the pixel clock is ~114.679 MHz, so within 5%.
When I read the Reference Manual, I see a Serializer clock limitation of 595 MHz. If I simply take my pixel clock of 109.19 MHz and multiply it by 7 (as implied by other threads Single Channel LVDS Display with 1920x1080@60Hz ), I get 764.33 MHz, which exceeds the specification.
I'm successfully getting video through my system. What gives?
By the way, I configured my DTS file for full 1920x1080p @ 60 Hz, and the system hung while loading the kernal.