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如何配置这个文件:P10xx-P20xxRDB_P2010_init_sram.tcl

Question asked by xu chen on Jun 14, 2016
Latest reply on Nov 14, 2016 by ufedor

以下为该文件官方给出的配置内容:

########################################################################################

# Initialization file for P10xx-P20xxRDB board with P2010 CPU

# Clock Configuration:

#       CPU:1200 MHz, CCB: 600 MHz,

#       DDR: 666 MHz, SYSCLK:  50 MHz

########################################################################################

 

 

variable CCSRBAR 0xFF700000

 

 

proc CCSR {reg_off} {

  global CCSRBAR

 

  return p:0x[format %x [expr {$CCSRBAR + $reg_off}]]

}

 

 

proc apply_e500v2_workaround {} {

  # After reset, e500 cores need to run before being able to enter debug mode.

  # Work-around: set a HW BP at reset address and run the core; after the core hits the BP, it enters debug mode

  # e500 cores need to have valid opcode at the interrupt vector

 

 

  variable SPR_GROUP "e500 Special Purpose Registers/"

 

 

  #######################################################################

  # Set a breakpoint at the reset address

  reg ${SPR_GROUP}IAC1 = 0xfffffffc

  reg ${SPR_GROUP}DBCR0 = 0x40800000

  reg ${SPR_GROUP}DBCR1 = 0x00000000

 

 

  # Run the core

  config runcontrolsync off

  go

  wait 50  

  config runcontrolsync on

  stop

 

 

  # Clear affected registers

  reg ${SPR_GROUP}DBSR  = 0x01CF0000

  reg ${SPR_GROUP}DBCR0 = 0x41000000

  reg ${SPR_GROUP}IAC1  = 0x00000000

  reg ${SPR_GROUP}CSRR0 = 0x00000000

  reg ${SPR_GROUP}CSRR1 = 0x00000000

}

 

 

proc init_board {} {

 

 

  global CCSRBAR

 

  ##################################################################################

  # disable Boot Page Translation Register

  mem [CCSR 0x20] = 0x00000000

 

 

  # Invalidate again BR0 to prevent flash data damage in case

  # the boot sequencer re-enables CS0 access

  mem [CCSR 0x5000] = 0x00001000

 

  ##################################################################################

  # configure internal SRAM at 0x00000000

 

 

  # L2CTL

  # bit 0 = 0 - L2E: L2 SRAM disabled

  # bit 1 = 1 - L2I: L2 flash invalidate

  # bit 2-3 = 10 - L2SIZ: = 512K

  # bit 13-15 = 010 - L2SRAM: One half is SRAM (256K)

  mem [CCSR 0x20000] = 0x60020000

 

 

  # L2SRBAR0

  # bit 0-17 = BASE addr: 0x00000000

  mem [CCSR 0x20100] = 0x00000000

 

 

  # L2SRBAREA0

  # bit 28-31 = EXTENTED BASE addr: 0x00000000

  mem [CCSR 0x20104] = 0x00000000

 

 

  # L2CTL

  # bit 0 = 1 - L2E: L2 SRAM enable

  mem [CCSR 0x20000] = 0xA0020000

 

  ##################################################################################

  #

  # Memory Windows

  #

  # 0xFF000000 0xFFFFFFFF LAW0 Local Bus NOR FLASH - 16M

  #   0xF8000000  0xF80FFFFF  LAW5    Local Bus NAND FLASH 1M

  #

  ##################################################################################

 

  # configure local access windows

  # LAWBAR0 - Local Bus

  # bit 8 - 31 = 0xFF000000 - base addr

  mem [CCSR 0xc08] = 0x000ff000

 

 

  # LAWAR0

  # bit 0 = 1 - enable window

  # bit 7-11 = 00100 - Local Bus

  # bit 26 - 31 =  011011 16M - size

  mem [CCSR 0xc10] = 0x80400017

 

 

  # LAWBAR5 - Local Bus

  # bit 8 - 31 = 0xF8000000 - base addr

  mem [CCSR 0xca8] = 0x000f8000

 

 

  # LAWAR5

  # bit 0 = 1 - enable window

  # bit 7-11 = 00100 - Local Bus

  # bit 26-31 = 010011 1M - size

  mem [CCSR 0xcb0] = 0x80400013

 

  ##################################################################################

  # configure Local Bus memory controller

 

 

  # CS0 - Flash

  # BR0 base address at 0xF8000000, port size 16 bit, GPCM, valid

  mem [CCSR 0x5000] = 0xFF001001

  # OR0 16MB flash size

  mem [CCSR 0x5004] = 0xFF000FF7

 

 

  # CS1 - NAND Flash

  # BR1 base address at 0xF8000000, port size  8 bit, FCM, valid

  mem [CCSR 0x5008] = 0xF8000C21

  # OR1 1MB size

  mem [CCSR 0x500C] = 0xFFF80396

 

 

  # LBCR

  mem [CCSR 0x50d0] = 0x40000000

 

 

  # LCRR

  mem [CCSR 0x50d4] = 0x80000008

}

 

 

proc P10xx_P20xx_P2010_init_core {} {

 

  global CCSRBAR

 

 

  variable SPR_GROUP "e500 Special Purpose Registers/"

  variable SSP_GROUP "Standard Special Purpose Registers/"

  variable CAM_GROUP "regPPCTLB1/"

  variable GPR_GROUP "General Purpose Registers/"

 

  ##################################################################################

  # move CCSR at 0xE0000000

  # CCSRBAR

  # bit 8 - 23 - BASE_ADDR

  mem [CCSR 0x0] = 0x000e0000

  set CCSRBAR 0xe0000000

 

 

  #######################################################################

  # invalidate BR0

  mem [CCSR 0x5000] = 0x00001000

 

  # ABIST off

  # L2ERRDIS[MBECCDIS]=1 L2ERRDIS[SBECCDIS]=1

  mem [CCSR 0x20E44] = 0x0000000C

 

 

  # activate debug interrupt and enable SPU

  reg ${SSP_GROUP}MSR = 0x02000200

 

  ##################################################################################

  #

  # Memory Map

  #

  #   0x00000000  0x0003FFFF SRAM            256K

  # 0xE0000000 0xE00FFFFF CCSRBAR Space    1M

  #   0xF8000000  0xF80FFFFF  LocalBus NAND FLASH 1M

  #   0xFF000000 0xFFFFFFFF  LocalBus NOR FLASH 16M

  #

  ##################################################################################

  # MMU  initialization

 

 

  # define 1MB    TLB1 entry 1: 0xE0000000 - 0xE00FFFFF; for CCSR Space, non cacheable

  reg ${CAM_GROUP}L2MMU_CAM1 = 0x500003CAFC080000E0000000E0000001

 

 

  # define 16MB  TLB1 entry 2: 0xFF000000 - 0xFFFFFFFF; for Local Bus, non cacheable

  reg ${CAM_GROUP}L2MMU_CAM2 = 0x70000FCAFC080000FF000000FF000001

 

 

  # define 256KB  TLB1 entry 3: 0x00000000 - 0x0003FFFF; for internal chip SRAM

  reg ${CAM_GROUP}L2MMU_CAM3 = 0x400001C0FC0800000000000000000001

 

 

  # define 1MB    TLB1 entry 7: 0xF8000000 - 0xF80FFFFF; for NAND, cache inhibited

  reg ${CAM_GROUP}L2MMU_CAM7 = 0x500003CAFC080000F8000000F8000001

 

 

  init_board

 

  ####################################################################

  ### interrupt vectors initialization

  #

  ###interrupt vectors in internal SRAM

 

  # IVPR (default reset value)

  reg ${SPR_GROUP}IVPR = 0x00000000

 

 

  # interrupt vector offset registers

  # IVOR0 - critical input

  reg ${SPR_GROUP}IVOR0 = 0x00000100

  # IVOR1 - machine check

  reg ${SPR_GROUP}IVOR1 = 0x00000200

  # IVOR2 - data storage

  reg ${SPR_GROUP}IVOR2 = 0x00000300

  # IVOR3 - instruction storage

  reg ${SPR_GROUP}IVOR3 = 0x00000400

  # IVOR4 - external input

  reg ${SPR_GROUP}IVOR4 = 0x00000500

  # IVOR5 - alignment

  reg ${SPR_GROUP}IVOR5 = 0x00000600

  # IVOR6 - program

  reg ${SPR_GROUP}IVOR6 = 0x00000700

  # IVOR8 - system call

  reg ${SPR_GROUP}IVOR8 = 0x00000c00

  # IVOR10 - decrementer

  reg ${SPR_GROUP}IVOR10 = 0x00000900

  # IVOR11 - fixed-interval timer interrupt

  reg ${SPR_GROUP}IVOR11 = 0x00000f00

  # IVOR12 - watchdog timer interrupt

  reg ${SPR_GROUP}IVOR12 = 0x00000b00

  # IVOR13 - data TLB errror

  reg ${SPR_GROUP}IVOR13 = 0x00001100

  # IVOR14 - instruction TLB error

  reg ${SPR_GROUP}IVOR14 = 0x00001000

  # IVOR15 - debug

  reg ${SPR_GROUP}IVOR15 = 0x00001500

  # IVOR32 - SPE-APU unavailable

  reg ${SPR_GROUP}IVOR32 = 0x00001600

  # IVOR33 - SPE-floating point data exception

  reg ${SPR_GROUP}IVOR33 = 0x00001700

  # IVOR34 - SPE-floating point round exception

  reg ${SPR_GROUP}IVOR34 = 0x00001800

  # IVOR35 - performance monitor

  reg ${SPR_GROUP}IVOR35 = 0x00001900

 

  # put a valid opcode at debug and program exception vector address

  mem v:0x00000700 = 0x48000000

  mem v:0x00001500 = 0x48000000

 

  ##################################################################################

  apply_e500v2_workaround

 

 

  ##################################################################################

  #

  # activate debug interrupt and enable SPU

  reg ${SSP_GROUP}MSR = 0x02001200

 

 

  ############

  #

  # time base enable

  # HID0

  reg ${SPR_GROUP}HID0 = 0x00004000

 

 

  # NAND Flash settings - FMR

  mem [CCSR 0x50E0] = 0x0000F020

 

  ######

  # CW debugger settings

  #

 

 

  #Trap debug event enable

  reg ${SPR_GROUP}DBCR0 = 0x41000000

 

 

  #  set the PC at the reset address (for debug-->connect)

  reg ${GPR_GROUP}PC = 0xFFFFFFFC

  # for debugging starting at program entry point when stack is not initialized

  reg ${GPR_GROUP}SP = 0x0000000F

}

 

 

 

 

proc envsetup {} {

  # Environment Setup

  radix x

  config hexprefix 0x

  config MemIdentifier v

  config MemWidth 32

  config MemAccess 32

  config MemSwap off

}

 

 

#-------------------------------------------------------------------------------

# Main                                                                         

#-------------------------------------------------------------------------------

 

 

envsetup

 

 

P10xx_P20xx_P2010_init_core

 

 

我想知道MMU  initialization部分如何配置?

例如以下配置:

# define 16MB  TLB1 entry 2: 0xFF000000 - 0xFFFFFFFF; for Local Bus, non cacheable

  reg ${CAM_GROUP}L2MMU_CAM2 = 0x70000FCAFC080000FF000000FF000001

1、为什么要把entry 2 配置成 Local Bus, 该寄存器每一位表示什么含义在什么文档里面能找到,我在P2020RM中没有找到其具体定义?

2、整个tcl文档有相关配置说明文档么?

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