K64 defines maximum rise/fall time of 3ns of TCLK, is there a minimum value too?
To specify the JTAG electricals, our JTAG design timing optimization and static timing analysis is performed with this specific 3.0 ns input transition times on all input pins, across process/voltage/temperature corners. This 3 ns value is an input to our timing environment and determines the internal delays through I/O pads and the transition times on the internal core outputs of those pads. So to clarify, the JTAG TCLK rise/fall time spec of 3 nsec is intended to inform customers to control the input transition times and not exceed this value in order for the other JTAG electrical input specs to remain valid.
in the DS this 3ns requirement is presented to TCLK signal only and not to any other JTAG inputs,
Could you please specify the measurment points for this rise/fall time?
Could you please specify the capacitacne and pull-up value which with them the 3ns value is valid?
Yes, the 3ns is really for signal TCLK as you emphsised. And as for the measurment point for the TCLK pins, please make reference the BSDL file of the K64.
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