I have a custom MIPI-CSI2 device implemented with FPGA and this passive TX PHY design( https://www.altera.com/en_US/pdfs/literature/an/an754.pdf )
This is a single lane device, transmitting 32bit user-defined datatype (type 0x30, virtual channel 0).
The MIPI-CSI clock is 160MHz and 320Mbps.
I set DPHY clock to // 150-160MHz :0x04 //159Mhz.
In my kernel driver, after mipi_csi2_reset(); the DPHY status is 0x610, but after turning on the FPGA, the DPHY status starts switching between 0x000 and 0x010.
According to 40.6.6 of the IMX6DQRM, 0x610 means:
1) "Clock Lane in Stop state
2) "Clock Lane module has NOT entered the Ultra Low Power state" (Not very sure about this one)
3) "Data Lane 0 in Stop state"
I've done some research, and I believe if the DPHY is operating normally, the status should be 0x310/0x300, is this correct?
I see on the scope that the CSI_CLK_HS_P and CSI_CLK_HS_N are both abour 100mV p-p, is this too low?
What have I missed that can cause DPHY not detecting MIPI-CSI DDR clock?