On "Understand Vybrid Architecture" cache access latency
Processor registers 1 cycle
On-chip L1 cache 1-2 cycles
On-chip L2 cache 8 cycles
Main memory, L3, dynamic RAM 30-100 cycles
Back-up memory, hard disk, L4 > 500 cycles
But I used DS-5 to measure cache access latency
L1 cache read hit 32 cycle, write hit 3 cycle
when LDR follows STR it becomes 71 cycle on hit
How does that happen?
Are there more accurate numbers of cache access latency for vybrid VF6xx processor?
I found that data caching was disabled by default, beside SCTLR.C what should I set to enable it?