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MPC8260 UPM and SRAM interfacing

Question asked by Supriyo Ganguly on Jun 10, 2016
Latest reply on Jun 14, 2016 by Serguei Podiatchev

We have been using MPC8260. We have connected UPM with SRAM 1MB through FPGA. Port size = 16bit. From processor address lines, data lines, CS, BS, bctl0 and UPMWAIT is connected to FPGA. PSDVAL, TA and TEA are connected to pull ups. We found that after assertion(low) and de-assertion(high) of UPMWAIT, sometimes CS is still asserted. What is the possible reason and solution to this issue?@

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