In the T4240RM.pdf, can find two register DDRx_TIMING_CFG_1[WRTORD], DDRx_TIMING_CFG_4[WRT], it seems the same, what is the difference?
Actually you could notice that descriptions of DDRx_TIMING_CFG_1[WRTORD] and DDRx_TIMING_CFG_4[WRT] are a bit different.
Basically the rule is as following, the DDR controlller automatically calculates time between WRITE and READ commands to meet tWTR (WRTORD) specification if READ hits the same memory bank (same CS). DDRx_TIMING_CFG_4[WRT] defines how many extra clock cycles will be added to that time. We recommnd to set this field to 0, i.e. default. This means that DDRx_TIMING_CFG_0[WRT] defines number of extra clock cycles. In turn we also recommend to set DDRx_TIMING_CFG_0[WRT] = 0, this will provide the fastest write-to-read turnaround timing.
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