SCI issue

[jberri]

I am using the following demo board M68Demo0908GB60, which comes with a 32kHz crystal.  I am using the external 32K crystal, but my goal is to set the SCI to 9600 baud rate.  I am using the bean inspector, but no matter what I set for my baud rate divisor, I can't get 9600?  On the CPU side I have set the clock frequency to 0.032 MHz, clock divider to be 1 and FLL to be enabled, I just thought I would need to share this info, incase someone can see the obvious, that I have missed.

Thank you,

jberri

[jberri]

I am using processor expert V6.1 the evaluation.

[ProcessorExpert]

Please could you provide more details about your project? What version of Processor Expert do you use? Do you use the Processor Expert or the Device Initialization tool? If you use Processor Expert, which type of the bean do you use? Init_SCI or Aynchroserial Hi-level bean?

In the attachement you can find an example project for the latest PE V3.02 (PE 3.02 servicepack installed into CW6.1). It shows how to set the 9600 baud rate for GB60 CPU with both the AsynchroSerial bean and Init_SCI bean.

Information how to find the version of the currently installed Processor Expert is in the weblink below: www.processorexpert.com/support/faq/hc08

Processor Expert Support Team
www.processorexpert.com

[jberri]

Demo board, M68DEMO908GB60, using processor expert CW 6.1 eval, bean CPU MC9S08GB60CFU, I enabled the external clock, set external clock enabled, clock freq. 0.032768, clock range set to low freq., high speed clock set to external clock, clock divider set to 64, which sets the internal clock bus to 0.16384 MHz, I set the FLL to enabled.

If I use the following formula : Busclk = Baud rate [SBR12BR0] x 16 = 153,600, I used 1 for [SBR12BR0].

The internal clock bus I am currently showing is 0.16384 MHz, no matter what divider I use I can't get 0.15360 MHz, which would give me 9600 in the SCI bean.

At the SCI bean I have set the following: baud rate divisor 1, but under the internal clock bus I get 10240 baud, is I try other values, they still don't give me the 9600 baud I am looking for.

What other info can I provide, to help with my issue?

Thank you.

[ProcessorExpert]

There is no possibility to set Internal bus clock to 0.15360 MHz with the 32.768 kHz crystal so it´s not possible to set exactly 9600 baud with SCI prescaler 1. The closest value which is possible to set is 9637.647 baud, which is in usual tolerance of 1.5% for asynchronous communication.

Better way to set the Internal bus clock to the requested value is to set the "Clock divider" property to "Auto select" and then to fill requested value into the Internal bus clock property. The possible closest value will be set. Then you should set the "Baud rate divisor" property to set the closest value of 9600 baud. Use for example internal bus clock 5.24 MHz and SCI divider 34.

More information about calculation the frequency for the SCI modul you can find in the "Clock path" option in the in the timing dialog of the "Baud rate" property in the Asynchroserial bean. (In the "Bean Inspector" window of the "Asynchroserial" bean set the "Items Visibility"option to ADVANCED to the "Clock path" option show). The "Clock path" shows how the Baud rate is calculate in the both Init_SCI bean and Asynchroserial bean.  

For More details on CPU timing please see the CPU datasheet.

Processor Expert Support Team
www.processorexpert.com

[jberri]

I used the 5.24MHz and the divider 34 and the value is 9637.647 baud.  I would like to know what you use to calculate the 5.24MHz?  Also what did you use to calculate the 34 divider?

I believe the baud rate is ok, you are right about the 1.5% tolerance, I look it up.

Thank you so much......    please let me know the above, I hate to be blind as to where numbers come from.

[ProcessorExpert]

This is determined by the hardware, you can see it in the CPU datasheet. The SCI periphery needs a input clock, which is an integer multiple of 0.1536MHz to be able to generate baudrate 9600. However, the Internal Clock Generator module can produce only limited set of frequencies based on the 32kHz crystal. The output frequency of the ICG module is 0.32768 * 64 * ICG_multiplier/ICG divider. The multiplier can have values 4, 6, 8, 10, 12, ..., 18, the divider has values 1, 2, 4, 8, ... 128.

It is neccesary to find a busclock, which is close to 0.1536 multiple. Generally, the higher the bus clock is, the higher is the SCI divider and the lower as an error caused by the bus clock not being a multiple of 0.1536. Attached spreadsheet gives you a table of all possible baudrates for 32kHz crystal and corresponding SCI dividers for 9600 baud.

Please note that if you don't want to deal with individual prescalers, you can use Asynchroserial bean, where you can set 9600 bauds and PE computes all prescalers automaticaaly. If the Asynchroserial bean is not able to set this baudrate (it reports an error), you just keep adjusting the CPU bus clock until the Asynchroserial bean doesn't report an error.

Processor Expert Support Team
www.processorexpert.com