In the hardware design, we connect 4 MT41K256M16 chips to DDR0 controller and no ECC. when do DDR initialization, find that it will pop out "Automatic calibration error", why?
Most probably the error happens due to problems with write leveling calibration. Write leveling requires some initialization parameters that greatly depend on the physical DDR implementation on the board. For example, T4240RDB configuration in uboot assumes using of DDR3 DIMM. Discrete DDR3 chips may require different setup due to different PCB layout.
Thanks a lot for your help!
Yes, we use discrete DDR3 chip. could you please help to tell me about the related parameters? or could you please help to recommend some documentations for configure and debug T4240 DDR3?
Meanwhile, I find some clue in the windriver P4080 DDR configure code(I guess P4080 and T4240 use the same DDR controller IP?), it said that freescale recommend to shutdown the calibrate function by writting some value to 0xFd30 and 0xF54, but these two registers is not mentioned in the p4080 reference manual. is it correct?
No, mentioned issue does not relate to the T4240. However the T4240 has similar erratum:
Description: During the receive data training, the DDRC may complete on a non-optimal setting.
Impact: With non-optimal training results, data corruption could be detected or initialization may fail.
Workaround: Before setting MEM_EN, ensure the following:
If operating at... Then set DEBUG_29 to a value of...
For this erratum DEBUG_29 is at CCSRBAR + DDR_OFFSET + f70h.
I would recommend to start DDR debugging at minimal working data rate, 1066MT/s - 1333MT/s.
Currenly have a T4240RDB that hangs during uboot when DDR controller interleaving is left at the default 3way_4KB value. I have noticed that debug_29 for all controllers is equal to 0x00700064. This value doesn't match any of the values you mentioned. Please advise.
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