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ADC clock

Question asked by Siyu Wu on Jun 7, 2016
Latest reply on Jun 8, 2016 by Siyu Wu


According to the manual, EQADC engine on the MPC5777c is being fed with PER_CLK. Does that imply the ADC0/1 also have their clocks sourced from PER_CLK?  This is confusing because according to the second screenshot, ADC0/1 have their clock sourced from "system clock". Is this the real "system clock" like core clock or is it referring to EQADC system clock which is PER_CLK?  


There are also numerous places in the manual saying stuff like

     "Due to legacy reasons, the EQADC will always wait 120 ADC

     clocks before issuing the first conversion command following

     the enabling of one of on-chip ADCs

And many some other places refer EQADC operations with ADC clock cycles, which kinda imply EQADC clock and ADC clock are the same thing.

So, is the ADC clock PER_CLK according to the first screen shot or is it sourced from the actual system clock?


Thank you!!


Screen shot 1

Screen shot 2