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Unable to read from register CPSR. Target is in reset

Question asked by Branden Sherrell on Jun 7, 2016
Latest reply on Jun 14, 2016 by Serguei Podiatchev

My goal is to enable Secure Boot without permanently flashing the SRKH registers. From other questions I have posted to this community and documentation I have found, I am led to believe this is possible by using a JTAG debugger and a few configuration tweaks. Most notably, setting BOOT_HO=1 in the RCW allegedly allows for register tweaks prior to executing the validation code (ISBC, etc).

 

Currently I have all components flashed to the device, including a RCW with BOOT_HO=1. As expected, when powered all four cores are held in reset. At this time I would expect to be able to access the core's registers and write the temporary SRKH value to the mirror registers. However, I am unable to access any memory of the device in this state.

 

I am not using the CodeWarrior TAP at the moment. I am using an ARM DSTREAM and the DS5 IDE. Are there related configuration parameters necessary to access CPU registers while in reset? Please forgive me if this is an obvious question; I have done little JTAG debugging leading up to this. I know this setup works as I can set BOOT_HO=1 and access registers by interrupting the CPU -- it's just when the cores are in reset that I am having trouble.

 

The feedback from DS5 that I am getting is `Unable to read from register CPSR. Target is in reset`.

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