On the MCF5275 datasheet, under section 8.7 <Processor Bus Output Timing Specifications>, Table 13 B6a/B6b/B6c - Clockout timing indicates only maximum timing.
Is there any typical timing and tests results to show, if any?
Well, yes, the signals are spec'd this way so that they always transition with respect to a perfectly symmetrical clock. For example for asynchronous devices, it isn't really a concern anyway since the /CS isn't sampled with respect to a clock edge anyway. For synchronous devices that only sample signals on the rising edge, then you can add wait states to the bus cycle to compensate for the possibility of the device not seeing the chip select on the first possible clock edge and so on.
A couple of points on the timing shown in the data sheet.
First, a design should always be proved to obey the "worst case" timing, and not be designed for "typical". That's the only way to guarantee reliability on a production run in different temperatures and so on. That's usually the "maximum".
Second, let's say I want to know "what's the worst case setup time from A[23-0] to CSn" as that might be a parameter I have to match for a memory chip.
"B6a CLKOUT high to chip selects valid" is given as a MAXIMUM of "0.5 Tcyc + 5ns".
"B8 CLKOUT high to address (A[23:0])" is given as a MAXIMUM of "9ns" from the SAME clock edge.
A naive reading of those two figures could be that the minimum Chip Select time might be ZERO and therefor might happen AFTER A[23-0] transitions, giving a negative setup time. The diagram implies (but does not STATE) that the chip-selects transition after the falling clock, and the "0.5 Tcyc" implies that.
Nothing in the Data Sheet clears that up.
You have to read the Data Sheet in conjunction with the Reference Manual. Section "16.3 Bus Characteristics" says:
where all bus
operations are synchronous to the rising edge of CLKOUT, and some of the bus control signals
(BS, OE, and CSn) are synchronous to the falling edge,
That proves there's Tcyc/2 setup time between these signals, with the 5ns and 9ns being the worst case from those clock edges.
You mentioned that for asynchronous devices no need to consider the timings for w.r .to clock, but the input data for read cycle happen on rising clock edge, so we should maintain the required data setup time?
To calculate the data setup time, I should know the b6 a timings.
I measured over 6 boards, the b6a timing is 8.6ns w.r.to clk, as per data sheet the worst case value is 11.575ns, is this value change by ageing?
How do you arrived this 11.575ns, by any testing?
> How do you arrived this 11.575ns, by any testing?
Not just testing. The device is *DESIGNED* to operate within its published specifications using theory and low level modelling.
Have you heard about the "four corners"? They're the points of minimum and maximum temperature, coupled with minimum and maximum supply voltage. So "hot and low voltage" may be slower than "cold and high voltage". These temperature and voltage limits are listed in the Data Sheet.
Then there's the pad loading. Is the pad driving an open circuit or running at its maximum drive level (5mA or 2mA depending on the pins)? Are you running high or low drive capacitance (50pF)? Is the pin programmed to Low or High Drive Strength?
So the maximum time is probably worst case temperature, voltage and maximum DC and AC pad loading.
Then there's process variation. Different chips in different batches will have slightly different characteristics. This will be controlled, tested and measured, and statistics applied to guarantee that under the worst case conditions the worst chip that passed the production tests will meet the published specifications.
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