Cannot disable the cache in region 9 of Kinetis K61

[mauriziocolella]

I have some external peripheral on CS0 configured in region 9 the is cached for default.

So I tried to disable the cache in region 9 of Kinetis K61. I correctly changed the LMEM_PCCRMR register putting 0 into bits 12 and 13. After this I can read back the value from that register but I noticed that cache is still enabled.

I always get 16 consecutive read cycle on first access to CS0 while successive access are not output on the flexbus.

I moved CS0 configuration from region 9 to 11 (non cacheable) and this fixed my problem.

Why cache on region 9 cannot be disabled? Is there something wrong with my procedure?

Best Regards

M. Colella

[isaacavila]

Hello,

MQX does enable the cahce in the _bsp_init function (init_bsp.c file). It is probably best for you to modify the region settings before that first call to enable cache. In fact, MQX is already modifying some of the regions, so I would recommend you to make any additional changes in same spot:

/** Cache settings **/
    /* After reset is set maximal configuration for cache regions. We can only degrade cache (write_back to write trough to non cacheable)*/
    /* Only one half of DDR has ability for write back cache type ,therefore we change both DDR regions to write trough type*/
    LMEM_PSCRMR = (LMEM_PSCRMR & ~LMEM_PCCRMR_R7_MASK & ~LMEM_PCCRMR_R8_MASK) | LMEM_PCCRMR_R7(0x2) | LMEM_PCCRMR_R8(0x2) ;
    LMEM_PCCRMR = (LMEM_PCCRMR & ~LMEM_PCCRMR_R7_MASK & ~LMEM_PCCRMR_R8_MASK) | LMEM_PCCRMR_R7(0x2) | LMEM_PCCRMR_R8(0x2) ;
    /*folowing 2 functions enable caches (instruction and data cache) and invalidate caches*/
    _ICACHE_ENABLE(0);
    _DCACHE_ENABLE(0);

I hope this helps!

Regards,

Isaac