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P2020NXE2KFC DDR3-667 clocking

Question asked by Stefan Vranken on Jun 6, 2016
Latest reply on Jun 6, 2016 by Bulat Karymov

Hello,

For peace of mind, do you see anything wrong in next clocking setup ?

P2020NXE2KFC

K : cpu frequency (H=800, K=1000, M=1200,N=1333)

F : ddr speed = datarate in Mbps (F = 667; H=800)  << mclk_freq Mhz = (333;400)

 

platform CCB frequency = 66.66 (sys-clk) x 6 (pll-ccb) ~ 400 Mhz

CCB-freq range for Core[1000M] : 266 Mhz min ; 533 Mhz max

 

core:CCB clk ratio=2.5:1

core-freq= 400 x 2.5 = 1000 Mhz

 

ddr3-datarate 667 Mbps is higher than ccb-clk frequency.

P2020-ddr-controller cannot be used in synchronous mode (its default mode)

use asynchronous mode : DDR-CLK-input = 66.66 Mhz

DDR: DDR-CLK ratio = 10:1  >> DDR-controller-internal-clock = 666.60 Mhz >> DDR-MCK-out=333.30 Mhz

ok, ddr3-sdram chip  min freq = 303 Mhz

 

AN4261-hw-design-checklist-rev4

Par 6.1.2 DDR Clocking Range

Table 12, note-4

Asynchronous mode requirement = ok :  ddr controller MCK output =333.3 Mhz is less than or equal to CCB-CLK = 400 Mhz.

 

Regards,

Stefan

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