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DDR3L is not working at above 800 MT/s with T1040

Question asked by gourav jain on Jun 6, 2016
Latest reply on Jun 10, 2016 by Bulat Karymov

Hi guys,

My custom board which is based on T1040RDB, has DDR3L module MT4KTF25664HZ-1G6E1. This DDR is wroking properly at clock 400  MHz (800 MT/s data rate) while giving error once the clock goes above 400 MHz. ideally DDR should work upto 1600 MT/s.

 

DDR at 400 MHz:

U-Boot 2014.07 (May 16 2016 - 10:14:12)

CPU0:  T1040E, Version: 1.1, (0x85280011)

Core:  e5500, Version: 2.1, (0x80241021)

Clock Configuration:

       CPU0:1400 MHz, CPU1:1400 MHz, CPU2:1400 MHz, CPU3:1400 MHz,

       CCB:600  MHz,

       DDR:400  MHz (800 MT/s data rate) (Asynchronous), IFC:150  MHz

       QE:300  MHz

       FMAN1: 600 MHz

       QMAN:  300 MHz

       PME:   300 MHz

L1:    D-cache 32 KiB enabled

       I-cache 32 KiB enabled

Reset Configuration Word (RCW):

       00000000: 0c0c000e 0e000000 00000000 00000000

       00000010: 69000000 80000002 ec027000 21000000

       00000020: 00000000 00000000 00000000 00032000

       00000030: 00000000 00025a8f 00000000 00000000

Board: T1040-GCR

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM 4KTF25664HZ-1G6E1

GGG-Found timing match: n_ranks 1, data rate 833, rank_gb 0

        clk_adjust 4, wrlvl_start 6, wrlvl_ctrl_2 0x6060607, wrlvl_ctrl_3 0x8080807

2 GiB (DDR3, 64-bit, CL=6, ECC off)

Flash: 256 MiB

L2:    256 KiB enabled

Corenet Platform Cache: 256 KiB enabled

Using SERDES1 Protocol: 105 (0x69)

NAND:  0 MiB

MMC:   FSL_SDHC: 0

*** Warning - bad CRC, using default environment

DDR at above 400 MHz:

 

U-Boot 2014.07 (May 16 2016 - 10:14:12)

 

 

CPU0:  T1040E, Version: 1.1, (0x85280011)

Core:  e5500, Version: 2.1, (0x80241021)

Clock Configuration:

       CPU0:1400 MHz, CPU1:1400 MHz, CPU2:1400 MHz, CPU3:1400 MHz,

       CCB:600  MHz,

       DDR:533.333 MHz (1066.667 MT/s data rate) (Asynchronous), IFC:150  MHz

       QE:300  MHz

       FMAN1: 600 MHz

       QMAN:  300 MHz

       PME:   300 MHz

L1:    D-cache 32 KiB enabled

       I-cache 32 KiB enabled

Reset Configuration Word (RCW):

       00000000: 0c10000e 0e000000 00000000 00000000

       00000010: 69000000 80000002 ec027000 21000000

       00000020: 00000000 00000000 00000000 00032000

       00000030: 00000000 00025a8f 00000000 00000000

Board: T1040-GCR

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM 4KTF25664HZ-1G6E1

GCR-Found timing match: n_ranks 1, data rate 1350, rank_gb 0

        clk_adjust 4, wrlvl_start 7, wrlvl_ctrl_2 0x708080a, wrlvl_ctrl_3 0xa0b0c09

Waiting for D_INIT timeout. Memory may not work. (its stucking here).

 

 

 

pls  let me know where i need to debug??

 

--

Gourav

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