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P2041 e500mc MCSR[LDG] error without MCSR[LD]

Question asked by Mehmet Celik on Jun 6, 2016
Latest reply on Jun 6, 2016 by ufedor



We are using P2041 processor and we are receiving an error MCSR[LDG] without receiving MCSR[LD]. (MCSR[LD] is 0 but MCSR[LDG] is 1). In E500mc Core Reference Manual document, it is explained why this error bit would set when LD bit is set, but there is no explanation without LD bit. MCAR, MCARU, MCSRR0 and cache address generation registers are not set either. Can you give more information why LDG bit is set when LD bit of MCSR is 0? Is there a way to get the address of error occured during the attempt if applies?


Thank you...