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KL27 SPI1 FIFO using interrupt with non blocking write transfer and SDK 2.0

Question asked by Ben Houston on Jun 1, 2016
Latest reply on Jun 7, 2016 by Ben Houston

I have beating my head against the keyboard for the last couple of days on this.  Has anyone had success implementing the SPI1 FIFO on a KL2x series using the SDK 2.0???

 

I can get a non blocking write to work all day with SPI0, using the spi_interrupt.c example code provided with SDK 2.0, but have had no luck using SPI1.  For a write of 2 bytes, on the oscope, I see both bytes leaving and the Rx FIFO filled from the MOSI, but it hangs in the program.  The CSn goes low and high for both byte transfers and the clock looks good.

 

Stepping through the debugger in IAR indicates that the callback is never called and I hang in an infinite while loop waiting for the isMasterFinished to be set to true by the call back.

 

Here are my code snippets:

Defines:

#include "clock_config.h"

#include "fsl_spi.h"

#include "fsl_gpio.h"

/*******************************************************************************

* Definitions

******************************************************************************/

#define SPI_MASTER SPI1

#define SPI_MASTER_SOURCE_CLOCK kCLOCK_CoreSysClk

#define SPI_MASTER_IRQ SPI1_IRQn

#define SPI_MASTER_IRQHandler SPI1_IRQHandler

 

Initialization:

---snipit---

CLOCK_EnableClock(kCLOCK_PortD);

PORT_SetPinMux(PORTD, 4U, kPORT_MuxAlt2); /* PCS0 J1-9  */

PORT_SetPinMux(PORTD, 5U, kPORT_MuxAlt2); /* SCK  J1-11 */

PORT_SetPinMux(PORTD, 6U, kPORT_MuxAlt2); /* MOSI J2_18 */

PORT_SetPinMux(PORTD, 7U, kPORT_MuxAlt2); /* MISO J2-20 */

-------------

 

---snipit---

SPI_MasterGetDefaultConfig(&masterConfig);

SPI_MasterInit(SPI_MASTER, &masterConfig, CLOCK_GetFreq(SPI_MASTER_SOURCE_CLOCK));

SPI_MasterTransferCreateHandle(SPI_MASTER, &spiHandle, SPI_UserCallback, NULL);

 

Where:

void SPI_UserCallback(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData)

{

    isMasterFinished = true;

}

-------------   

 

Implementation:

xfer.txData = spiAddr;

xfer.rxData = receiveBuff;

xfer.dataSize = spiTxDataLength;

// Send out.

SPI_MasterTransferNonBlocking(SPI_MASTER, &spiHandle, &xfer);

// Wait send finished.

while (!isMasterFinished)

{

     // Program Hangs here when using SPI1.  For SPI0, this worked fine.

}

 

Any insight or encouraging words would be much appreciated.

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