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Hello, I intend to use IDT_6V49205B clock generator for P2020 but see that its rise/fall slew rate for PCIe ref_clk is too high

Question asked by Stefan Vranken on Jun 1, 2016
Latest reply on Oct 21, 2016 by Stefan Vranken

The IDT_6V49205B is a programmable clock generator (IDT Versaclock-6) tailored for freescale P10xx and P20xx.

However, looking at the AC-spec of its PCIe clock output I see "Rising/Falling Edge slew rate" = 4.1 V/ns typ and 5.7 V/ns max. This is higher than max 4 V/ns edge rate of P2020 SD_REF_CLK input (P2020 hw-spec  rev3, table-76)

This seems strange because IDT_6V49205B is tailored for P20xx ?

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