Our customer have a question about i.MX6DQ DDR design.
Please see Figure 3-9 in i.MX6 Hardware Development Guide (IMX6DQ6SDLHDG Rev.1).
We understand that this figure shows the reference layout of the decoupling capacitor with 4 DDR3 memories for T-topology.
Also reference board schematics show how much capacitance is needed with 4 chips DDR3 design for T-topology.
Actually, our customer will design i.MX6DQ platform with Fly-by-topology with 8 DDR3 memories.
So would you give us your advice about placement of decoupling capacitor similar as Figure 3-9, and how much capacitance is needed in this case?