AnsweredAssumed Answered

MPC5675K - Convert from Lock Step Mode to Decoupled Parallel Mode

Question asked by Gareth Franklin on May 31, 2016
Latest reply on May 31, 2016 by Petr Stancik

Hi,

 

I have a MPC5675K microprocessor that is configured in lock step mode and I want to change it back to decoupled parallel mode.

 

I wrote some software that sets the LSM_DPM user option bit in the shadow sector of the flash memory (see below) and then I run my clock configuration routine.

 

However, this does not work and the software hangs during the clock configuration routine. At the moment I cannot figure out what the problem is and why the code hangs.

 

Am I configuring the LSM_DPM user option bit correctly? Is my clock configuration routine ok? Any help would be most appreciated.

 

Regards,

 

Gareth

 

int main(void)

{

// ================ Main ==================

 

    SHADOWFLASH.NVUSRO.B.LSM = 0;            // set processor to DPM

 

    ClockConfig();                                                    //  configure clocks

}

 

 

 

void ClockConfig(void)

{

// ================ Clock Configuration and Run Modes ==================

    int wait = 0;

 

    // Initialise Run modes and Clock

    // Init sequence DRUN -> RUN0 -> RUN1 -> RUN0 -> RUN0

   

    ME.MER.R = 0x0000003D;                        // Enable DRUN, RUN0, RUN1 SAFE, RESET modes

   

    // Mode Transition to enter RUN0 mode:

   

    ME.RUN[0].R = 0x001F0030;                      // RUN0 cfg: 16MHzIRCON,OSC0OFF,PLL0OFF,PLL1OFF,syclk=16MIRC

    ME.MCTL.R = 0x40005AF0;                        // Enter RUN0 Mode & Key    

    ME.MCTL.R = 0x4000A50F;                     // Enter RUN0 Mode & Inverted Key

   

    while(ME.GS.B.S_XOSC == 0) {};              // Wait for mode entry to complete

   

    while(ME.GS.B.S_MTRANS == 1)                // Wait for mode transition to complete

       

    while(ME.GS.B.S_CURRENTMODE != 4) {};          // Check RUN0 mode has been entered

   

    // Select PLL sources

   

    CGM.AC3_SC.R = 0x01000000;                     // Select Xosc as PLL0 source clock

    CGM.AC4_SC.R = 0x01000000;                     // Select Xosc as PLL1 source clock

   

    // Set clock divider registers

   

    // set FMPLL0 to 80MHz - with xtal 20MHz

       

    CGM.FMPLL[0].CR.B.IDF = 0x7;                // FMPLL0 IDF=8 --> divide by 8

    CGM.FMPLL[0].CR.B.ODF = 0x0;                // FMPLL0 ODF=2 --> divide by 2

    CGM.FMPLL[0].CR.B.NDIV = 0x40;                // FMPLL0 NDIV=64 --> divide by 64

   

    // set FMPLL1 to 40MHz - with xtal 20MHz

 

    CGM.FMPLL[1].CR.B.IDF = 0x7;                // FMPLL1 IDF=8 --> divide by 8

    CGM.FMPLL[1].CR.B.ODF = 0x0;                // FMPLL1 ODF=2 --> divide by 2

    CGM.FMPLL[1].CR.B.NDIV = 0x20;                // FMPLL1 NDIV=32 --> divide by 32

   

    // Enable progressive clock switching

       

    CGM.FMPLL[0].CR.B.EN_PLL_SW = 1;            // PHI_PCS output only on PLL_0

   

    // Set peripheral run modes

   

    ME.RUNPC[0].R = 0x000000FE;                    // peripheral run in all modes

    ME.RUNPC[1].R = 0x00000000;                    // peripheral frozen in all modes

    ME.LPPC[0].R = 0x00000000;                    // peripheral frozen run in LP modes

   

    // Auxiliary clock settings

   

    CGM.SC_DC0.R = 0x00000000;                    // disable system clock 0

    CGM.AC0_DC0.R = 0x00000000;                    // disable Motor Control clk div by 1 

    CGM.AC1_DC0.R = 0x00000000;                    // disable aux clk 1 div by 1  

    CGM.AC2_DC0.R = 0x00000000;                    // disable aux clk 2 div by 1

   

    // Mode Transition to enter RUN1 mode

   

    ME.RUN[1].R = 0x001F0070;                   // RUN1 cfg: 16MHzIRCON, OSC0ON, PLL0ON, PLL1off, syclk=16M IRC  

    ME.MCTL.R = 0x50005AF0;                     // Enter RUN1 Mode & Key

    ME.MCTL.R = 0x5000A50F;                     // Enter RUN1 Mode & Inverted Key

   

    while (ME.GS.B.S_MTRANS == 1)                 // Wait for mode transition to complete

   

    while(ME.GS.B.S_CURRENTMODE != 5) {};       // Check RUN0 mode has been entered

   

    // Make sure the SRAM wait states are configured for fsys

   

    ECSM_0.MUDCR.R = 0x40000000;

    ECSM_1.MUDCR.R = 0x40000000;

       

    // Max divider when switching fsys from IRC to PLL0

       

    CGM.FMPLL[0].CR.B.ODF = 0x2;                // FMPLL0 ODF=2 --> divide by 8

 

    // Mode Transition to enter RUN0 mode:

   

    ME.RUN[0].R = 0x001F0074;                   // RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,PLL1off,syclk=PLL0        

    ME.MCTL.R = 0x40005AF0;                     // Enter RUN0 Mode & Key      

    ME.MCTL.R = 0x4000A50F;                     // Enter RUN0 Mode & Inverted Key

   

    while(ME.GS.B.S_MTRANS == 1)                    // Wait for mode transition to complete

   

    while(ME.GS.B.S_CURRENTMODE != 4) {};       // Check RUN0 mode has been entered

   

    CGM.FMPLL[0].CR.B.ODF = 0x1;                // FMPLL0 ODF=0 --> divide by 4

   

    for(wait = 0;wait < 275;wait++) {};            // delay for the VDD reg to stabilize otherwise on the EVB, low voltage 1.2 VDD destructive reset might occur

       

    CGM.FMPLL[0].CR.B.ODF = 0x0;                // FMPLL0 ODF=0 --> divide by 2

   

    // Mode Transition to enter RUN0 mode:

   

    ME.RUN[0].R = 0x001F00F4;                    // RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,PLL1ON,syclk=PLL0           

    ME.MCTL.R = 0x40005AF0;                     // Enter RUN0 Mode & Key     

    ME.MCTL.R = 0x4000A50F;                     // Enter RUN0 Mode & Inverted Key

   

    while(ME.GS.B.S_MTRANS == 1)                // Wait for mode transition to complete

   

    while(ME.GS.B.S_CURRENTMODE != 4) {};       // Check RUN0 mode has been entered

   

    CGM.AC0_DC0.B.DE0 = 1;                        // enable aux clk 0 - MOTC_CLK for ADCs

    CGM.AC0_DC0.B.DIV0 = 0x0;                    // set aux clk 0 to divide by 1

    CGM.AC0_SC.R = 0x04000000;                    // select system PLL as clock source

   

    CGM.AC2_DC0.B.DE0 = 1;                        // enable aux clk 2 - FlexCAN CANPE_CLK

    CGM.AC2_DC0.B.DIV0 = 0x8;                    // set aux clk 2 to divide by 8

    CGM.AC2_SC.R = 0x04000000;                    // select system PLL as clock source

   

    // Set peripheral clock divisors   

   

    CGM.SC_DC0.R = 0x81830000;                    // peri set0 divide by 2, peri set1 divide by 4

   

    // Clock out

   

    CGM.OCDS_SC.R = 0x32000000;                    // divide by 1 set to system FMPLL

    CGM.OC_EN.B.EN = 0;                            // disable clock out - change to 1 (enable) if clock out function is required

   

    // SIU.PCR[233].R = 0x0600;                    // set output clock to port pin E20 and enable output buffer - remove comment to place clock out signal on ball E20

       

// end of mode and clock initialisation function

}

 

// Clear Fails Function

 

void ClearFails(void)

{

    uint16_t reset_register;

   

    if(RGM.FES.B.F_FCCU_SAFE)

    {

        reset_register = RGM.FES.R;

        ME.IMTS.R = 0x00000001;

        ClearCF();

        ClearNCF();

       

        RGM.FES.R = 0x0080; /* clear SAFE mode flag */

        /*RGM.DES.R = 0xFFFF;*/

       

        /* re-enter DRUN */

        ME.MCTL.R = 0x30005AF0; /* Enter DRUN Mode & Key */       

        ME.MCTL.R = 0x3000A50F; /* Enter DRUN Mode & Inverted Key */

    }

}

 

// ClearCF Function

 

void ClearCF(void)

{

    uint32_t i,a[4];

    for(i=0;i<2;i++)

    {

        FCCU.CFK.R = FCCU_CFK_KEY;

  

        FCCU.CFS[i].R = 0xFFFFFFFF;

 

        while(FCCU.CTRL.B.OPS != 0x3)

        {

           

        };      /* wait for the completion of the operation */

 

        a[i]=FCCU.CFS[i].R;

    }

}

 

// ClearNCF Function

 

void ClearNCF(void)

{

    uint32_t i,b[4];

    for(i=0;i<1;i++)

    {

        FCCU.NCFK.R = FCCU_NCFK_KEY;

        FCCU.NCFS0.R = 0x00001000;  /* clear NCF 12 */

        while(FCCU.CTRL.B.OPS != 0x3)

        {

       

        };              /* wait for the completion of the operation */

        b[i]=FCCU.NCFS0.R;

    }

}

Outcomes