I've been sitting on this problem for a while now. I have FEC (MII mode) working to communicate to my external PHY which I can communicate with using full duplex 100MBps. I currently have 16 RX Buffer Descriptors defined in software which i cycle through and mark as empty when read from (or in the case of the final bd, empty and wrap). This all works fine except that upon reception of data (polling FEC.EIR.B.RXF), the RX Buffer Descriptor pointed to by FEC.ERDSR.R updates multiple buffers with the data received. I am using buffer size 1536 and all buffers and buffer descriptors are 128-bit aligned as recommended. Has anyone experienced any issues like this?