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debug access to ddr_ctlr

Question asked by Jason Hendrix on May 27, 2016
Latest reply on Jun 4, 2016 by Jason Hendrix

Why can't we access the ddr controller without losing a JTAG connection?



  We're trying to bring up our custom board based on the LS1020a processor with DDR4 attached.  I've used the QCVS tool to generate initialization code that I'm using in my  bare-metal memory test app.  I also use the generated register values in U-Boot.  On the first access to the DDR controller registers, whether from my mem test app or from U-Boot, I lose my JTAG connection.  In CCS and in CodeWarrior, I can see that CCS is reporting a "ScanTimeout".  Do I have to do something special in order to access the DDR controller?  Does anyone know of any situations that can cause this kind of behavior?