SDK v2.0 Clock Configuration

[peterfurey]

Hi,

I'm trying to set up the clock configurations for a custom board using KDS_v3 and SDK_2.0_MK24FN1M0xxx12. The board has a MK24FN1M0VLL12 processor, an external 32MHz ECX-53B CPU crystal, and an external 32.768KHz ECX-31B RTC crystal. The only documentation that I've found to help me is the  K24 Sub-Family Reference Manual (K24P144M120SF5RM) and the Kinetis SDK v.2.0 API Reference Manual. I've come up with a first stab at a configuration but it hangs on start up at the following location.

main()->BOARD_BootClockRUN()->CLOCK_BootToPeeMode()->CLOCK_SetPbeMode():

(in CLOCK_SetPbeMode())

/* Wait for CLKST clock status bits to show clock source is ext ref clk */

while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=

           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))  // HANGS HERE

  {

  }

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

void BOARD_BootClockRUN(void)
{
    CLOCK_SetSimSafeDivs();

    CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);                   // 32000000U

    CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
                        &g_defaultClockConfigRun.mcgConfig.pll0Config);

    CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
                                  g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);

    CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);

    SystemCoreClock = g_defaultClockConfigRun.coreClock;
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

My configuration is as follows:

/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
    mcg_config_t mcgConfig;       /*!< MCG configuration.      */
    sim_clock_config_t simConfig; /*!< SIM configuration.      */
    osc_config_t oscConfig;       /*!< OSC configuration.      */
    uint32_t coreClock;           /*!< core clock frequency.   */
} clock_config_t;

/*******************************************************************************
* Variables
******************************************************************************/

/* Configuration for enter RUN mode. Core clock = 120MHz. */
const clock_config_t g_defaultClockConfigRun = {
    .mcgConfig =
        {
            .mcgMode = kMCG_ModePEE,             /* Work in PEE mode. */
            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
            .ircs = kMCG_IrcSlow,                /* Select IRC32k. */
            .fcrdiv = 0U,                        /* FCRDIV is 0. */

            .frdiv = 0U,
            .drs = kMCG_DrsLow,         /* Low frequency range. */
            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
            .oscsel = kMCG_OscselOsc,   /* Select OSC. */

            .pll0Config =
                {
                    .enableMode = kMCG_PllEnableIndependent, .prdiv = 0x7U, .vdiv = 0x6U,
                },
        },
    .simConfig =
        {
            .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
            .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
        },
    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
                  .capLoad = 0,
                  .workMode = kOSC_ModeExt,
                  .oscerConfig =
                      {
                          .enableMode = kOSC_ErClkEnable,
                      }},
    .coreClock = 120000000U, /* Core clock frequency */
};

Is there any other documentation on clock configuration or any examples using the above tools (or something similar)?

Or is there something obvious in the above configuration that I'm doing wrong?

Much thanks,

Peter

[sebestyenbela]

I think that there is an error in the CLOCK_BootToPeeMode function, because it calls the CLOCK_SetPbeMode function instead of CLOCK_SetPeeMode !?

Am I right ?

[nethanja]

Actually it's just a bug in the fsl_clock.c file. I've tested this with FSL Clock driver version 2.2.1 (check the fsl_clock.h header for this version info) on a MKV56F512.

So the bug is that EREFS bit in MCG_C2 is not getting set in the function CLOCK_SetPbeMode(..). 

To fix it, find the following line in CLOCK_SetPbeMode(..) in fsl_clock.c file:

MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */‍

and insert the following code right after it:

/* Enable External reference clock */
MCG->C2 |= MCG_C2_EREFS_MASK;‍‍

[peterfurey · Accepted solution]

Hi Xangjun,

I finally got the external oscillator working with the following configuration:

OSC_CR = 0x8E , ERCLKEN = 1, SC2P = 1, SC4P = 1, and SC8P = 1. (everything else cleared)

MCG_C2 = 0xE6, LOCRE0 =1, FCFTRIM =1, RANGE = 10, EREFS = 1, and LP = 1 (everything else cleared)

Regards,

Peter

[xiangjun_rong]

Hi, Peter,

if you use 32Mhz crystal, I think the EREFS bit in MCG_C2 register should be set so that the internal oscillaitor is used.

BR

Xiangjun rong

[xiangjun_rong]

Hi, Peter,

I suspect that the example code is developed based on the TWR-K24 tower board, which uses 8mhz crystal, but you use 32MHz crystal, so you have to change the MCG register value based on 32MHz crystal. As you know that the PLL input clock frequency is 2MHz~4MHz, so you have to set the MCG register so that the PLL input clock frequency is in the range.

Hope it can help you.

BR

Xiangjun Rong

[peterfurey]

Hello Xiangjun,

I tried creating a TWR-K24 tower board project but it's only available for SDK_1.3, not SDK_2.0. I tried to translate the generated code for this project but it didn't give me any success. I tried your other recommendations also but I don't see a way to set HGO and clear EREFS with the given SDK_2.0 mode API. Do you know how to do this?

Thank you,

Peter

[xiangjun_rong]

Hi, Peter,

In SDK1.3, we provide a lot of Hal function, which enable you manipulate the bits in peripheral register. But for SDK2.0, you can manipulate bits in peripheral register directly.

for example, if you want to set the HGO, you can use the code;

MCG->C2|=0x04; //seting  HGO

MCG->C2&=~(0x04); //clearing  HGO

If you want to use driver, you can to check the components of the g_defaultClockConfigRun structure in clock_config.c.

Hope it can help you

BR

Xiangjun Rong

[xiangjun_rong]

Hi,

I think the follwoing configuration is correct:.prdiv = 0x7U, .vdiv = 0x6U. The PLL input frequency is 32MHz/(7+1)=4MHz. The PLL output is 4Mhz*(30)=120Mhz.

Regarding your issue that the core stick to the line:

while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=

           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))  // HANGS HERE

It seems that the OSC configuration may be incorrect.

Pls check the OSC_CR register, the ERCLKEN should be cleared, because you use crystal instead of clock source.

BTW, I think you should check the HGO and EREFS bit in MCG_C2, the HGO should be set, EREFS bit should be cleared.

BR

XiangJun Rong

[peterfurey]

Hello Xiangjun,

Are you sure that the EREFS should be cleared in MCG_C2? The reference manual describes this field as such:

"External Reference Select

Selects the source for the external reference clock.

See the Oscillator (OSC) chapter for more details.

0 External reference clock requested.

1 Oscillator requested."

Thank you,

Peter