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Flexbus performance issue

Question asked by Viktors Snicarevs on May 25, 2016
Latest reply on Jun 5, 2016 by Hui_Ma

Hi! I am working Flexbus connection between mk22 micro and FPGA and trying to achieve maximum throughput in both directions. The configuration is 32 bit address and 32 bit data multiplexed, no wait states, auto-acknowledge.

First I have configured it to run at 40 MHz with core clocked at 120MHz. By looking on signals with logic analyzer I have recognized that instead of theoretical 4 cycles for read or write I am achieving only 5 cycles for read and 6 cycles for write.

When I clocked down the processor to 100 MHz and Flexbus speed to 50 MHz it runs 6 cycles for read and 7 cycles for write.

I have also confirmed that control register values are what I expect them to be.

Any consideration why this would be happening?


Addition: while running at 40MHz/120MHz if I add 1 wait state it runs at 5 cycles read or write (as expected).