LVDS MUX control of i.MX6Solo

[宗標廖]

Hello, community

As we know, there is only one IPU on i.mx6solo,so the source for LVDS0/1 is either DI0 or DI1.

But in i.mx6solo reference manual, bit6~9 of the GPR3 (IOMUXC_GPR3) is described as bellow.

What does it mean by 'LVDS source is LCDIF'?

Best Regards,

ZongbiaoLiao

[art · Accepted solution]

The LVDS0/1 MUX bits setting of 0b10 (LVDS0/1 source is LCDIF) is non-functional on the i.MX6Solo/DualLite SoCs, since there is no LCDIF module on these SoCs. Initially, it was projected to populate the LCDIF module on the i.MX6Solo/DualLite SoCs for the unification with the i.MX6SoloLite SoC that doesn't have IPU at all, however, finally, the LCDIF module has been rejected on these SoCs. So, this setting is non-functional on the i.MX6Solo/DualLite SoCs, just disregard it.

Have a great day,
Artur

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[宗標廖]

i.MX Community​

Could you give me a relpy?

Thank you!