各位前辈，我现在想配置恩智浦kinetis系列的KW30Z在低功耗VLPS模式使用外部参考32MHzOsc。根据用户参考手册中说明在VLPS模式下想要让外部参考32MHzOsc工作需要把DCDC配置成continuous mode。我的问题是，由于我们的硬件原理图设计不满足DCDC正常工作，我把DCDC配置成bypass 模式，同时把DCDC配置成continuous mode，这样是否能让外部参考32MHzOsc工作？
Could you please explain the problem in English?
Hi I have develop the power mode very low power stop(VLPS) that will be woken up by the low power timer (LPTMR) clocked by external 32MHz reference oscillator. Based on your reference manual, if i want the external 32MHz reference oscillator to work under the VLPS power mode , I must guarantee the inner DCDC configured for continous mode. However, our inner DCDC hardware design is same with your bypass configuration circuit from your reference manual. Based on the above, the continous mode of DCDC could make the external 32MHz OSC work under VLPS powermode ? Or there is another solution? Expecting your reply.
Yes, you are right the DCDC in continuous mode could make the external 32 MHz OSC work under VLPS, you have to configure the register DCDC_REG0, see the next picture.
See more details, check the reference manual
If you have problems with DCDC modes let me know
Hi Mario Just as you say, the DCDC in continuous mode by means of configuring the register DCDC_REG0 could make the external 32 MHz OSC work under VLPS. But if the peripheral circuit of the DCDC is bypass mode just as the picture below, then the external 32MHz OSC wouldn't work under VLPS, would it? Unfortunately, our circuit is designed as picture below. Is there any solution that we could make the external 32MHz OSC work under VLPS and meanwhile we don.t need modify the circuit?Expecting your reply!
The biasing is enable to reduced power, also limits the maximum operation frequency of the device. That frequency limit is why the 32MHz oscillator should be off.
The biasing is disable in VLPs mode when DCDC is configures for continuous mode, in that case the oscillator can be enabled for use by the ratio logic.
Note: Biasing is disable the current drain is going to be higher than what is normally expected for VLPS mode.
Could you please share the application purpose? Why do you want to configure in biasing mode?
Hi Mario My ultimate purpose is to ensure that the external 32MHz reference oscillator clocks the low power timer(LPTMR) under the VLPS mode. There are two reasons: The first is that the LPTMR is used for TDMA, so the reference clock source of the LPTMR must be accurate and only the external 32MHz reference oscillator is suitable; The second is to reduce power, so I choose the VLPS mode that allow the external 32MHz reference oscillator to work by configuring the DCDC in continuous mode. Based on the above reason, I configured the DCDC in continuous mode. But the integrated development environment tells me the hardware error when it executes the code configuring the DCDC in continuous mode. When I check our circuit, I find that the peripheral circuit of the DCDC inner the MCU is designed to bypass mode just as your reference manual. I judge that the peripheral circuit of the DCDC is in buck mode or boost mode is precondition of configuring the DCDC in continuous mode. So, am I right? If my judgement is right , we have to modify our circuit design, or there is another solution by which we could not modify the circuit and achieve our ultimate purpose. Expecting your help.
Is there any reason of using VLPS mode, could you comment about your final application? Why VLPS is required?
Even if you set the device in buck mode to allow 32MHz in VLPS mode, your power consumption would be higher than in normal VLPS mode. Moreover, 32MHz ref oscillator frequency would be limited.
If you would like to achieve lowest power consumption, then you should set your board to work in buck mode, DC-DC in Buck mode allows KW4x to operate from a single coin cell battery with a significant reduction of peak Rx and Tx current consumption. Moreover, KW4x requires 32kHz external crystal to allow radio to enter into DSM to be able to enter in low power modes between ADV interval as well as connection intervals. In addition to this, low power mode that you should select is the LLS3 mode in which you can retain all SRAM and retain stack at wake up event. A wake up event could be LPTMR, GPIO or other module supported by the LLWU.
The next document can help you with the different power modes and details about the LLS3
You can use as reference the next example of low power configuration
Note: The examples are in IAR
Hope it helps
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