My T2080RDB base custom board is using 0xE0 & 0x36 combination of SERDES protocol. With this combination of protocol selection, SRIO is 4x. How can I make SRIO to 1x in this SERDES protocol
Just use only SerDes2 lane D (3).
Thanks for the fast response...
From your answer, I assume that you are saying to connect only one lane (one physical connection) between processor(host) and FPGA(agent), rest three lines should not be connected between host and agent.
But I want to know, is there a way to control and select a particular lane from software? By configuring any registers or so?
Thanks & Regards
> is there a way to control and select a particular lane from software?
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