I have a simple experiment set up to accept an analog input and route directly to a DAC output. Using a signal analyzer I am then measuring the frequency response. The gathering of the ADC result and assignment to DAC output are performed within a 4kHz interrupt. I get significant phase response differences between these two scenarios:
1) ADC is in continuous scan mode. Upon entering the ISR, the result is read and assigned to the DAC output. With this I get approx. 180 degrees of lag at 2.4kHz.
2) ADC is in single scan mode. Upon entering the ISR, the scan is triggered by writing to the SSE bit. I then wait until I see the completion flag CF, then assign to the DAC output. With this I get approx. 180 degrees of lag at 1.2kHz.
Can anyone help me understand why this would be? Is there anything HW related that would cause this? Is there a trick to initialization? I can't see anything in the documentation that would suggest an extra interrupt cycle delay.
Any/all suggestions are appreciated,