Explanation of i.MX28 ICOLL vector generation

[jschoen]

I’m trying to chase down what appears to be a spurious interrupt on the i.MX28 processor.  Looking for clarification on the operation of ICOLL and inconsistencies in the vector generation.  A dump of the ICOLL registers after ISR entry shows the following:

HW_ICOLL_RAW0  0x0

HW_ICOLL_RAW1   0x1

HW_ICOLL_RAW2  0x0

HW_ICOLL_RAW3  0x0

HW_ICOLL_VECTOR  0xC0

HW_ICOLL_CTRL 0x0

HW_ICOLL_VBASE  0x0

HW_ICOLL_STAT 0x7F

HW_ICOLL_DEBUG 0x0

HW_ICOLL_VECTOR indicates the source bit number is 3 (vdda_brownout_irq).  HW_COLL_RAWx indicates that it is source 32 (emi_error_irq).   HW_ICOLL_STAT indicates that it is source 127 (pinctrl0_irq). 

Can someone clarify if we are interpreting the ICOLL registers correctly and explain the inconsistencies?

Thanks in advance.

[Yuri]

Hello,

  i.MX28 ICOLL supports interrupts nesting, allowing multiple interrupts.

Please refer to section 5.2.1 (Nesting of Multi-Level IRQ Interrupts)

of the i.MX28 Reference Manual. In particular, please look at NOTE of this

section, where "phantom interrupt" is mentioned. perhaps the problem concerns

with improper sequence in ISR.

Have a great day,
Yuri

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