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DDR3 memory calibration in a imx6d board

Question asked by Angel Ivan Castell Rovira on May 13, 2016
Latest reply on Dec 23, 2016 by Ivan Castell



I'm trying to configure DDR3 RAM memory to start the calibration test in a i.MX6D board.



The problem is I don't see the output generated by the stress test in the debug console UART1. This is the first time I try to do this task, so probably I havent configured some register properly.



The memory connected in my custom board is a 1GB Micron with Part Number: MT41J256M16HA-125:E. According to datasheet, the micron memory has this configuration:


    Configuration:  32 Meg x 16 x 8 banks

    Refresh count:  8K

    Row addressing: 32K

    Bank addressing: 8

    Column addressing: 1K

    Page size: 2KB

    CK: 1.25ns

    CL: 11

    Target RCD-RP-CL: 11-11-11

    RCD (ns): 13.75

    RP (ns): 13.75

    CL (ns): 13.75

    Data Rate (MT/s): 1600

    RAS (MIN) Idd: 28

    RC (MIN) Idd: 39


Hardware is designed with just one single Chip Select.


In order to setup control registers I am using I.MX6DQSDL DDR3 Script Aid V0.10.xlsx aid script with this values:



    Device Information


    Manufacturer:                   Micron

    Memory part number:             MT41J256M16HA-125:E

    Memory type:                    DDR3-800

    DRAM density (Gb):              2

    DRAM Bus Width:                 16

    Number of Banks:                8

    Number of ROW Addresses:        15

    Number of COLUMN Addresses:     10

    Page Size (K):                  2

    Self-Refresh Temperature (SRT): Normal

    CAS READ latency (CL)           11

    tRCD=tRP=CL (ns)                13,75

    tRC Min (ns)                    39

    tRAS Min (ns)                   28



    System Information


    i.Mx Part:                      i.Mx6D

    Bus Width:                      32

    Density per chip select (Gb):   8

    Number of Chip Selects used:    1

    Total DRAM Density (Gb):        8

    DRAM Clock Freq (Mhz):          400

    DRAM Clock Cycle Time (ns):     2,5

    Address Mirror (for CS1):       Disable



    SI Configuration


    DRAM DSE Setting - DQ/DQM (ohm):        48

    DRAM DSE Setting - ADDR/CMD/CTL (ohm):  48

    DRAM DSE Setting - CK (ohm):            48

    DRAM DSE Setting - DQS (ohm):           48

    System ODT Setting (ohm):               60



I am not sure if all these values are ok.


After translating generated to mwh/mww phys instructions, I can initialize DDR3 memory via netcat:


    $ nc localhost 3333

    > ddr_init


After initializing RAM with register values generated by the aid tool, I am able to read/write single RAM addresses:


    > mww 0x10000000 0x1234567

    mww 0x10000000 0x1234567

    > mdw 0x10000000

    0x10000000: 01234567


After that, I try to load the stress test tool 'ddr-test-uboot-jtag-mx6dq.elf' into internal RAM memory:


    $ arm-none-eabi-gdb

    > target remote localhost:3333

    > load ddr_stress_tester_jtag_v2.52/ddr-test-uboot-jtag-mx6dq.elf

    > cont


Process completes wthout any output error, but I don't see anything on the debug console (configured at 115200, 8N1).


I will appreciate any help on this.


Thank you in advance!