board: imx6q_sabresd;
version: u-boot-2009.08;
patch:0001-Enable-uboot-logo-for-HDMI-LCD-and-LVDS.patch
Dear Community,
i want to show logo on my 1280x1024 lcd panel, it uses lvds split mode in kernel, my kernel shows normal(LVDS_CLK:54M). Now, I need to show logo when system start up. But I found a strange problem when I patch the 0001-Enable-uboot-logo-for-HDMI-LCD-and-LVDS.patch to u-boot-2009.08. The LVDS0_CLK and LVDS1_CLK is about 74M no matter what the DISPLAY_PIX_CLOCK is.
#define DISPLAY_WIDTH | 1280 | ||
#define DISPLAY_HEIGHT | 1024 | ||
#define DISPLAY_BPP | 32 | ||
#define DISPLAY_IF_BPP | 24 | // RGB24 interface |
#define DISPLAY_HSYNC_START | 248 | ||
#define DISPLAY_HSYNC_END | 48 | ||
#define DISPLAY_HSYNC_WIDTH | 112 |
#define DISPLAY_VSYNC_START | 38 | ||
#define DISPLAY_VSYNC_END | 1 | ||
#define DISPLAY_VSYNC_WIDTH | 3 |
#define DISPLAY_PIX_CLOCK | 107964480 |
#define LVDS_SPLIT_MODE
kernel, 1280*1024
{ | |
"LDB-SXGA", 60, 1280, 1024, 9260, | |
248, 48, | |
38, 1, | |
112, 3, | |
0, | |
FB_VMODE_NONINTERLACED, | |
FB_MODE_IS_DETAILED,}, |
Hi jie
at that file one can find how it is produced:
ipu_setup()
...
+#ifdef IPU_OUTPUT_MODE_LVDS
+#ifdef LVDS_SPLIT_MODE
+ if (DI == 0)
+ clk_config(CONFIG_REF_CLK_FREQ, DISPLAY_PIX_CLOCK * 7 / 2, LVDS_DI0_CLK);
+ else if(DI == 1)
+ clk_config(CONFIG_REF_CLK_FREQ, DISPLAY_PIX_CLOCK * 7 / 2, LVDS_DI1_CLK);
clock produced by function config_lvds_clk() and also LVDS0,1_CLK are generated by dividing
by 3.5 if in split mode as described in attached document sect.20.6.1 Data serialization clocking
Best regards
igor
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Hi,igor
According to Figure 20-3 in iMX6_Firmware_Guide.pdf, I choose 540 PFD by setting CS2CDR: ldb_di0_clk_sel=3. However, I can't find what the 540 PFD derive from. Would you give me some advise to find and set it?
Hi,igorpadykov
Thanks for reply. Here is the info printed by u-boot.
config_ipu_lvds_clk: freq = 377875680.
config_ipu_lvds_clk: set pll3_pfd1 clock to 378MHz, divider = 22.
As you said, the lvds clk is 378/3.5 = 108M. In spilt mode , the should be the 54M. But I find the lvds clk is 75M in oscillograph. Is there something wrong in my include/configs/mx6q_sabresd.h?