Dear Wang,
can you help me, this question has bothered me for a long time,this is picture:
it is gree, but the logo picture is this:
what is wrong? and this is my head file:
//#define IPU_OUTPUT_MODE_HDMI
#define IPU_OUTPUT_MODE_LVDS
// #define IPU_OUTPUT_MODE_LCD
#ifdef IPU_OUTPUT_MODE_LVDS
// For LVDS, 1920*1080 resolution, dual channel
#define DISPLAY_WIDTH 1920
#define DISPLAY_HEIGHT 1080
#define DISPLAY_BPP 32
#define DISPLAY_IF_BPP 24 // RGB24 interface
#define DISPLAY_HSYNC_START 80
#define DISPLAY_HSYNC_END 68
#define DISPLAY_HSYNC_WIDTH 12
#define DISPLAY_VSYNC_START 15
#define DISPLAY_VSYNC_END 15
#define DISPLAY_VSYNC_WIDTH 8
#define DISPLAY_PIX_CLOCK 139526400 //(DISPLAY_HSYNC_START + DISPLAY_HSYNC_END + DISPLAY_HSYNC_WIDTH + DISPLAY_WIDTH) *
(DISPLAY_VSYNC_START + DISPLAY_VSYNC_END + DISPLAY_VSYNC_WIDTH + DISPLAY_HEIGHT) * refresh rate (60Hz)
#define LVDS_SPLIT_MODE // For dual channel split mode.
#define DISPLAY_VSYNC_POLARITY 1
#define DISPLAY_HSYNC_POLARITY 1
#define DISPLAY_CLOCK_POLARITY 1
#define DISPLAY_DATA_POLARITY 0
#define DISPLAY_DATA_ENABLE_POLARITY 1
#define IPU_NUM 1 // 1 for IPU1, 2 for IPU2.
#define DI_NUM 0 // 0 for DI0, 1 for DI1.
#define LVDS_PORT 0 // 0 for LVDS0, 1 for LVDS1.
#define DI_CLOCK_EXTERNAL_MODE //When clock external mode was defined, the DI clock root will be PLL3 PFD1,
//without this macro, the DI root clock is IPU internal clock.
can you help me? what should i do? what is info do you need? tell me.
wating for your reply?
thank you.
fulinux.
Dear Wang,
i did what he said, but the lcd panel screen is white, what should i do?
