Can proved sample code about that how does system enter LPU_RUN mode and go back to DRUN(RUN0..3) mode. I hope backup some data or system when the Z4a core enter standby mode. And then recover it when the Z4a core enter DRUN(RUN0..3) mode.
You have nice sample in AN4830, called "lp_stop"... Read chapter 2.7 - Low Power: STOP mode.
You can also check power domains - chapter 7.2 in MPC5748GRM. This is to assure that your configuration will preserve RAM that you need, since only 8k of the RAM is always preserved, the rest is dependent on RD1, RD2 & RD3 setting. Be aware that 512kB of RAM resides in PD2 power domain and it is always completely powered OFF during STANDBY and LPU modes.
I had saw AN4830 that use Wake Up model to recover. My project uses FlexCAN( pretended networking ) to wake up, but the Z4a core is still STANDBY mode when receive correct CAN message. The Z2 core transfer LUP_STOP mode to LUP_RUN mode when receive correct CAN message. How does the Z4a core enter RUN mode with the Z2 core.
See chapter "8.6 Exit from LPU Modes" in MPC5748GRM.
I work on the example right now. Please be patient, I will provide you the example as soon as possible.
Thank you very much!
I have the same question, can you help it?
I tried to create some example, which demonstrate, how to switch micro from LPU_RUN to DRUN, but I am not sure, if my solution is correct. Now I wait for answer from application engineer. This is the reason why I did not publish this example yet.
But you can try and as soon as I have any information, I will update the example or confirm the solution I have created.
PS: please ignore the name of the project. It is based on earlier project and I did not rename it.
Is there any update on your LPU example code?
I tried to confirm the working of LPU_RUN --> DRUN, but it seems that the device fall into some unknown state.
Also, I cannot see any mode transition without debugger, does the erratum e9200 is related with this problem?
Hope to receive your feedback
the latest version of my example is above in this thread. I have tried many procedures, but I found only one workaround used in the example.
I have the same problem as you describe. After LPU_RUN -> DRUN mode transition, core z2 is reset correct, but z4a is in some indefinite state and it is not possible to connect to it. I tried with debugger and also without debugger, but the behavior is always the same.
If I have some time, i try to investigate it deeper, but for now I am little bit busy. If you do some tests and find out any relevant information, please write me back.
Retrieving data ...