Hi,
I am going to use MT48LC4M32B2 – 1 Meg x 32 x 4 Banks(32 bit, 8-Column) to work with K65F MCU. Based on table 35-11 below:
Table 35-11. SDRAM Controller to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
SDRAM Controller Pins A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
Row 15 14 13 12 11 10 9 17 18 19 20 21 22 23
Column 2 3 4 5 6 7 8 16 CMD
SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
On this chip, address is defined as: A0~~A10,A11,BA0,BA1.
Could you tell me how to connect to BA0, BA1?
1) SDRAM_A20-->A10, SDRAM_A21-->BA0, SDRAM_A22-->BA1, SDRAM_A23-->A11? Or
2) SDRAM_A20-->A10, SDRAM_A21-->A11, SDRAM_A22-->BA0, SDRAM_A23-->BA1?
Thanks,
Chrisite
Solved! Go to Solution.
Hi, Chrisite,
You use the SDRAM, which has 1 Meg x 32 x 4 Banks(32 bit, 8-Column), the required address lines is A0~A19, the total address lines is 20, the column address lines is 8, of course, the row address lines is 12. The Table 35-11 gives the address map between the SDRAM controller and SDRAM.
SDRAM controller address:A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
SDRAM address A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
Hope it can help you
BR
Xiangjun Rong
Hi, Chrisite,
You use the SDRAM, which has 1 Meg x 32 x 4 Banks(32 bit, 8-Column), the required address lines is A0~A19, the total address lines is 20, the column address lines is 8, of course, the row address lines is 12. The Table 35-11 gives the address map between the SDRAM controller and SDRAM.
SDRAM controller address:A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
SDRAM address A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
Hope it can help you
BR
Xiangjun Rong