David Trotter


Discussion created by David Trotter on May 10, 2016

Hi There. We are trying to use the SGTL5000 to process (eq) analogue audio in this mode:


line-in -> ADC -> DAP -> DAC -> HP out


The chip is configured to use the PLL with a 8Mhz asynchronous clock input. (we use the onboard clock in PLL mode when testing with the DEV board).


We have an amplifier connected to the HP output with 26db of gain driving the loudspeaker. All gain settings at default (0db ADC gain, 0db DAC gain. 0db HP gain) and running 24bit 44.1kHz audio sampling.


Set up like this, the output from the codec is REALLY noisy.. it's not just white noise but "garbled" digital noise as well. You can hear this massive about of noise in the speaker which is totally unacceptable. We are using the SGTL5000 DEV (EVM) board to confirm that the noise is coming from the IC and not our own PCB.


The noise becomes acceptable when you turn the DAC down to -10 to -20db... but there is not enough signal at this level to drive the amplifier. The noise is not present in the original audio - if we plug the audio source directly into the amplifier the noise is very low.


Even running in bypass mode Line-In -> HPout there is still too much noise.


I have tried:


1) Bypassing the MIC input with capacitor

2) Turning dithering on and off

3) Various gain settings

4) Turning the ADC HPF on and off


Am I doing something wrong or is this just a noisy chip? I can provide all the setup data if this helps.


Thanks in advance