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T1024 IFC NOR Flash Interface timing question

Question asked by Matthew Charman on May 9, 2016
Latest reply on May 30, 2016 by Pavel Chubakov

The question I have is about the T1024 NOR Flash interface timing. We are interfacing to the Micron NOR flash (JS28F00AM29EWHA) which is the same as on the Reference Board Design for this processor.

 

  • The concern we have is with regards to Hold Time for a Read Cycle (Figure 23-38 from the T1024 Reference Manual).
  • Per the datasheet, the T1024 requires 5ns hold time (based on a 200MHz ip_clk)
  • The NOR flash (JS28F00AM29EWHA) doesn’t provide any hold time after OE, CE or ADDR are negated

                                          

In summary the T1024 datasheet doesn’t clearly show the relationship between when the data is sampled by the T1024, and when OE, CE or ADDR are negated by the T1024 – this information is required to show that the hold time requirement is met.

 

Are you able to clarify?

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