Other conditions are:
Even queue entries have: CONT=0, BITSE=0, DT=0, DSCK=0,
Odd queue entries have: CONT=0,BITSE=1,DT=0,DSCK=0.
The above gets 24 bits from and A/D converter every two queue entries.
NEWQP and ENDQP always get 4 queue entries. They start at 0 & 3 and are changed after several thousand samples to 4 & 7 then 8 & 11 and finally 12 & 15 respectively.
The QSPI runs correctly until the first change then the QSPI interrupts come very slowly, about 50 times slower while the shift clock (SCK) is weird and sporadic.