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I.MX6 DDR3 Dual Rank Design guidelines

Question asked by Suhas DK on May 6, 2016
Latest reply on May 12, 2016 by Artur Petukhov

HI,

 

In one of our new design we are using DDR3 memory with dual rank design. Flyby topology is used to route the signals. The maximum DDR3 Clock frequency supported by the I.MX6 processor  is 533 MHz.

 

Currently we have done with routing of data/address/control signals and also we have length matched the data signals with minimum tolerance of +or-10 mils data signal is routed from processor to top DDR3 Device then to bottom DDR3).There is presence of signal stub around 400 mils when routing data lines from top DDR3 to Bottom DDR3,

The total etch length of data signal is 1600 Mils. etch length from processor to TOP DDR3 is 1200 Mils from top DDR3 to Bottom DDR3 is around 400 Mils.

 

We would like to know whether 400 Mil stub on data signal is allowed, if not what is the maximum allowed stub length on data signals.

 

And also please share the guidelines, layout examples regarding dual rank memory technology which uses flyby routing topology.

 

Thanks & Regards,

Suhas D K.

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