I am using I.mx6 processor, In that there are two clock pins are available to use as Input/output clock (CLK1 & CLK2),
1. I want to generate 100MHZ clock frequency on CLK1 pin.
2.Anyone can suggest me clear steps to achieve this and which are all registers I need to use.
First, you have to select the desired pad for the CLKO1 signal as per the Table 18-2 of the i.MX6Dual/Quad Reference Manual Rev.3 document. To do that, you have to correspondingly configure the corresponding IOMUXC_SW_MUX_CTL_PAD_(pad_name) register. Then, you have to select the correct source and correct divide ratio
for the CLKO1 signal in the CCM_CCOSR register. For example, you can select PLL1 as the source and set the divide ratio to 4 or 5 depending on what frequency, 800 or 1000MHz, the PLL1 runs on.
The document, mentioned above, can be found on the i.MX6Quad Documentation web page:
Have a great day,
Artur
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Hi Artur Petukhov sir
processor:I.mx6 QUAD processor.
I want to generate 100MHZ clock on CLK2_P or CLK2_N (PIN NO: B25 & B36) ,
1. please suggest me which IOMUX pad register I need to use.
2.I want to select PLL6(ENET ref clock) as source for CLK01 , But there is no option in CCM_CCOSR register to choose this PLL. So which PLL you prefer.
Thank you in advance..
CLK2_P/N are not independent signals, but this is the differential pair of LVDS-type signals, not a regular I/O. These signals have no pin multiplexing options. For the information on the possible clock sources for this clock differential pair, refer to the description of the CCM_ANALOG_MISC1n register (Section 18.7.19) in the Reference Manual document.
Hi Artur Petukhov sir
Thank you for your fast reply
If I set clock source in LVDS1_CLK_SEL in CCM_ANALOG_MISC1n register . Can I get that clock output in CLK1P/N
You also have to configure these pins as outputs by setting the LVDSCLK1_OBEN bit and clearing the LVDSCLK1_IBEN bit in the same CCM_ANALOG_MISC1n register.
Hello sir
Once again make me sure that..,,
whether I get clock output on PIN CLK1_P/N or PIN LVDS1_CLKP/N.
These are just different names for the same thing.
Hello sir
How can I generate 100MHZ clock on LVDS0_CLK_P/N(PIN No: B62 & B63).
Hello sir..
You are telling both are same , But In I.MX6 QUAD processor PIN diagram, there is separate PINS are available in that name. On which PIN I will get output.
1.LVDS1_CLK_P -> PIN: B13
2.LVDS1_CLK_N -> PIN: B14
3.CLK2_P -> PIN: B35
4.CLK2_N -> PIN: B36
Please tell me on which should check the clock output , when I configure in CCM_ANALOG_MISC1n register.
Hi Artur Petukhov sir
I am using IOMUXC_SW_MUX_CTL_PAD_SD1_CLK Pad register to configure the MUX. Is it correct or some other register I need to use.
I am choosing this mode:-
011 ALT3 — Select signal GPT_CLKIN
Here they have mentioned CLKIN , can I use it as CLKOUT.
To make me able to provide you with an accurate answer, please first specify what exactly i.MX6 processor (Quad, Dual, DualLite, Solo, SoloLite, SoloX, UltraLite) do you use.
Best Regards,
Artur
Hi Artur Petukhov sir .
I am using I.mx6 Quad processor,
In that there are two clock pins are available to use as Input/output clock (CLK1 & CLK2),
1. I want to generate 100MHZ clock frequency on CLK1 pin.
2.Anyone can suggest me clear steps to achieve this and which are all registers I need to use.
Thank you in advance..
Hi..,
i.mx6 quad processor,
Actually Clock generation problem was resolved , now I am getting 100MHZ clock from CLK1 PIN. I need one more help,
1. I want to configure a PIN as GPIO mode (output mode). Can you please suggest me how configure a pin as GPIO mode.