we are working on T1024RDB. we understand that the NAND flash is accessed using IFC internal SRAM buffers rather than accessing directly. we saw the configuration details in T1024RM.
we want to know that, if we NAND flash is not directly accessed, and it is accessed through IFC internal SRAM buffer, what happens when unexpected power cycle happened to processor? is the data in IFC internal SRAM buffer will be updated to NAND flash before the processor power off? or the data in SRAM buffers will be lost?